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Peter J. Nicholas

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  • Philadelphia, PA, US
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Patents Grantslast 30 patents

  • Information Patent Grant

    Voltage level translator circuit
    • Patent number 8,536,925
    • Issue date Sep 17, 2013
    • Agere Systems LLC
    • Dipankar Bhattacharya
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Mode latching buffer circuit
    • Patent number 8,362,803
    • Issue date Jan 29, 2013
    • LSI Corporation
    • Peter J. Nicholas
    • H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

  • Information Patent Application

    Mode Latching Buffer Circuit
    • Publication number 20120212256
    • Publication date Aug 23, 2012
    • LSI Corporation
    • Peter J. Nicholas
    • H03 - BASIC ELECTRONIC CIRCUITRY