Peter Lahnor

Person

Dresden, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Interconnect structure for semiconductor devices
- Patent number 8,138,538
- Issue date Mar 20, 2012
- Qimonda AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for reducing charge trapping in high-k dielect...
- Patent number 7,894,240
- Issue date Feb 22, 2011
- Qimonda AG
- Michael Beck
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for forming an integrated circuit, including openings in a...
- Patent number 7,776,759
- Issue date Aug 17, 2010
- Qimonda AG
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of determining the endpoint of a planarization process
- Patent number 6,932,674
- Issue date Aug 23, 2005
- Infineon Technologies Aktientgesellschaft
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Grant
Defect-minimizing, topology-independent planarization of process su...
- Patent number 6,893,968
- Issue date May 17, 2005
- Infineon Technologies AG
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of planarizing substrates
- Patent number 6,827,635
- Issue date Dec 7, 2004
- Infineon Technologies Aktiengesellschaft
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Grant
CMP process
- Patent number 6,821,894
- Issue date Nov 23, 2004
- Infineon Technologies AG
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and semiconductor wafer configuration for producing an align...
- Patent number 6,787,431
- Issue date Sep 7, 2004
- Infineon Technologies AG
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor substrate holder for chemical-mechanical polishing co...
- Patent number 6,695,687
- Issue date Feb 24, 2004
- Infineon Technologies AG
- Mark Hollatz
- B24 - GRINDING POLISHING
Information Patent Grant
Method of simultaneously polishing a plurality of objects of a simi...
- Patent number 6,689,691
- Issue date Feb 10, 2004
- Infineon Technologies AG
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Grant
Method for improving the readability of alignment marks
- Patent number 6,153,492
- Issue date Nov 28, 2000
- Infineon Technologies AG
- Stephan Wege
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Structuring a Layered Stack
- Publication number 20100099253
- Publication date Apr 22, 2010
- Ulrich Baier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
- Publication number 20100090264
- Publication date Apr 15, 2010
- QIMONDA AG
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Reducing Charge Trapping in High-K Dielect...
- Publication number 20100054022
- Publication date Mar 4, 2010
- QIMONDA AG
- Michael Beck
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
- Publication number 20090142916
- Publication date Jun 4, 2009
- QIMONDA AG
- Heike Prenz
- B24 - GRINDING POLISHING
Information Patent Application
INTEGRATED CIRCUIT HAVING A MEMORY
- Publication number 20080217672
- Publication date Sep 11, 2008
- QIMONDA AG
- Martin Popp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A...
- Publication number 20070286945
- Publication date Dec 13, 2007
- QIMONDA AG
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PLANARIZING SUBSTRATES
- Publication number 20040185756
- Publication date Sep 23, 2004
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Application
METHOD OF DETERMINING THE ENDPOINT OF A PLANARIZATION PROCESS
- Publication number 20040176015
- Publication date Sep 9, 2004
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Application
Defect-minimizing, topology-independent planarization of process su...
- Publication number 20030190809
- Publication date Oct 9, 2003
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and semiconductor wafer configuration for producing an align...
- Publication number 20030096488
- Publication date May 22, 2003
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor substrate holder for chemical-mechanical polishing co...
- Publication number 20020177394
- Publication date Nov 28, 2002
- Mark Hollatz
- B24 - GRINDING POLISHING
Information Patent Application
Method of simultaneously polishing a plurality of objects of a simi...
- Publication number 20020146877
- Publication date Oct 10, 2002
- Peter Lahnor
- B24 - GRINDING POLISHING
Information Patent Application
CMP process
- Publication number 20020036181
- Publication date Mar 28, 2002
- Peter Lahnor
- H01 - BASIC ELECTRIC ELEMENTS

Peter Lahnor

Person

Patents Grantslast 30 patents

Interconnect structure for semiconductor devices

Method and apparatus for reducing charge trapping in high-k dielect...

Methods for forming an integrated circuit, including openings in a...

Method of determining the endpoint of a planarization process

Defect-minimizing, topology-independent planarization of process su...

Method of planarizing substrates

CMP process

Method and semiconductor wafer configuration for producing an align...

Semiconductor substrate holder for chemical-mechanical polishing co...

Method of simultaneously polishing a plurality of objects of a simi...

Method for improving the readability of alignment marks

Patents Applicationslast 30 patents

Method for Structuring a Layered Stack

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES

Method and Apparatus for Reducing Charge Trapping in High-K Dielect...

APPARATUS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

INTEGRATED CIRCUIT HAVING A MEMORY

METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A...

METHOD OF PLANARIZING SUBSTRATES

METHOD OF DETERMINING THE ENDPOINT OF A PLANARIZATION PROCESS

Defect-minimizing, topology-independent planarization of process su...

Method and semiconductor wafer configuration for producing an align...

Semiconductor substrate holder for chemical-mechanical polishing co...

Method of simultaneously polishing a plurality of objects of a simi...

CMP process