Peter Pöchmüller

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated DRAM memory device
- Patent number 7,203,123
- Issue date Apr 10, 2007
- Infineon Technologies AG
- Peter Pöchmüller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test system and test structure for testing an integrated circuit an...
- Patent number 7,193,426
- Issue date Mar 20, 2007
- Infineon Technologies AG
- Peter Pöchmüller
- G01 - MEASURING TESTING
Information Patent Grant
Method and device for generating digital signal patterns
- Patent number 7,117,403
- Issue date Oct 3, 2006
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory circuit
- Patent number 7,113,417
- Issue date Sep 26, 2006
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast synchronous digital circuits, particularly...
- Patent number 7,062,690
- Issue date Jun 13, 2006
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for reading and for checking the time position of...
- Patent number 6,871,306
- Issue date Mar 22, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Address counter for addressing synchronous high-frequency digital c...
- Patent number 6,862,702
- Issue date Mar 1, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating control signals for testing hi...
- Patent number 6,839,397
- Issue date Jan 4, 2005
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast integrated digital circuits, in particular...
- Patent number 6,721,904
- Issue date Apr 13, 2004
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration and method for producing test signals for testing a m...
- Patent number 6,618,836
- Issue date Sep 9, 2003
- Infineon Technologies AG
- Peter Pöchmüller
- G01 - MEASURING TESTING
Information Patent Grant
Circuit configuration for repairing a semiconductor memory
- Patent number 6,601,194
- Issue date Jul 29, 2003
- Infineon Technologies AG
- Wilfried Dähn
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing fast synchronous semiconductor circuits
- Patent number 6,556,492
- Issue date Apr 29, 2003
- Infineon Technologies AG
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for carrying out burn-in processing operations of sem...
- Patent number 6,535,009
- Issue date Mar 18, 2003
- Infineon Technologies AG
- Peter Pöchmüller
- G01 - MEASURING TESTING
Information Patent Grant
Field-effect-controlled transistor and method for fabricating the t...
- Patent number 6,515,319
- Issue date Feb 4, 2003
- Infineon Technologies AG
- Dietrich Widmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and configuration for compensating for parasitic current losses
- Patent number 6,490,191
- Issue date Dec 3, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for testing chips using a printed circuit board
- Patent number 6,472,892
- Issue date Oct 29, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G01 - MEASURING TESTING
Information Patent Grant
Method of testing memory cells with a hysteresis curve
- Patent number 6,456,098
- Issue date Sep 24, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for regulating the power consumption of an in...
- Patent number 6,448,749
- Issue date Sep 10, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated memory having memory cells and reference cells
- Patent number 6,438,053
- Issue date Aug 20, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing a memory cell having a floating gate
- Patent number 6,396,752
- Issue date May 28, 2002
- Infineon Technologies AG
- Jens Lüpke
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with at least two plate segments
- Patent number 6,314,018
- Issue date Nov 6, 2001
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells and reference cells
- Patent number 6,310,812
- Issue date Oct 30, 2001
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated dynamic semiconductor memory having redundant units of m...
- Patent number 6,304,499
- Issue date Oct 16, 2001
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory configuration with a built-in-self-test
- Patent number 6,295,237
- Issue date Sep 25, 2001
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Integrated DRAM memory device
- Publication number 20060120200
- Publication date Jun 8, 2006
- Peter Pochmuller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated dynamic memory cell and method for fabricating it
- Publication number 20050233538
- Publication date Oct 20, 2005
- Infineon Technologies AG
- Peter Pochmuller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test system and test structure for testing an integrated circuit an...
- Publication number 20050156612
- Publication date Jul 21, 2005
- Peter Pochmuller
- G01 - MEASURING TESTING
Information Patent Application
Integrated memory circuit
- Publication number 20050108459
- Publication date May 19, 2005
- Peter Pochmuller
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory and method for operating an integrated memory
- Publication number 20030156453
- Publication date Aug 21, 2003
- Peter Pochmuller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of testing a memory cell having a floating gate
- Publication number 20010024392
- Publication date Sep 27, 2001
- Jens Lupke
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for regulating the power consumption of an in...
- Publication number 20010006339
- Publication date Jul 5, 2001
- Peter Pochmuller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configuration for testing chips using a printed circuit board
- Publication number 20010005141
- Publication date Jun 28, 2001
- Peter Pochmuller
- G01 - MEASURING TESTING

Peter Pöchmüller

Person

Patents Grantslast 30 patents

Integrated DRAM memory device

Test system and test structure for testing an integrated circuit an...

Method and device for generating digital signal patterns

Integrated memory circuit

System for testing fast synchronous digital circuits, particularly...

Method and device for reading and for checking the time position of...

Address counter for addressing synchronous high-frequency digital c...

Circuit configuration for generating control signals for testing hi...

System for testing fast integrated digital circuits, in particular...

Configuration and method for producing test signals for testing a m...

Circuit configuration for repairing a semiconductor memory

System for testing fast synchronous semiconductor circuits

Configuration for carrying out burn-in processing operations of sem...

Field-effect-controlled transistor and method for fabricating the t...

Method and configuration for compensating for parasitic current losses

Configuration for testing chips using a printed circuit board

Method of testing memory cells with a hysteresis curve

Circuit configuration for regulating the power consumption of an in...

Integrated memory having memory cells and reference cells

Method of testing a memory cell having a floating gate

Integrated memory with at least two plate segments

Integrated memory having memory cells and reference cells

Integrated dynamic semiconductor memory having redundant units of m...

Semiconductor memory configuration with a built-in-self-test

Patents Applicationslast 30 patents

Integrated DRAM memory device

Integrated dynamic memory cell and method for fabricating it

Test system and test structure for testing an integrated circuit an...

Integrated memory circuit

Integrated memory and method for operating an integrated memory

Method of testing a memory cell having a floating gate

Circuit configuration for regulating the power consumption of an in...

Configuration for testing chips using a printed circuit board