Peter Pochmuller

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configuration for the transmission of signals between a data proces...
- Patent number 7,466,761
- Issue date Dec 16, 2008
- Qimonda AG
- Peter Pöchmüller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and probe card configuration for testing a plurality of inte...
- Patent number 6,853,206
- Issue date Feb 8, 2005
- Infineon Technologies AG
- Michael Hübner
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory and method for operating an integrated memory
- Patent number 6,822,913
- Issue date Nov 23, 2004
- Infineon Technologies AG
- Peter Pöchmüller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test configuration and test method for testing a plurality of integ...
- Patent number 6,762,611
- Issue date Jul 13, 2004
- Infineon Techologies AG
- Michael Hübner
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated dynamic memory, and method for operating the integrated...
- Patent number 6,741,491
- Issue date May 25, 2004
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing device for testing a memory
- Patent number 6,661,718
- Issue date Dec 9, 2003
- Infineon Technologies AG
- Carsten Ohlhoff
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated clock generator, particularly for driving a semiconducto...
- Patent number 6,646,937
- Issue date Nov 11, 2003
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory and memory configuration with a plurality of memo...
- Patent number 6,542,430
- Issue date Apr 1, 2003
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM configuration
- Patent number 6,487,108
- Issue date Nov 26, 2002
- Infineon Technologies AG
- Peter Pöchmüller
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and probe card configuration for testing a plurality of inte...
- Publication number 20040124863
- Publication date Jul 1, 2004
- Infineon Technologies AG
- Michael Hubner
- G01 - MEASURING TESTING
Information Patent Application
Configuration for the transmission of signals between a data proces...
- Publication number 20030074490
- Publication date Apr 17, 2003
- Peter Pochmuller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated dynamic memory, and method for operating the integrated...
- Publication number 20030031043
- Publication date Feb 13, 2003
- Peter Pochmuller
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for reading and for checking the time position of...
- Publication number 20020160558
- Publication date Oct 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
Testing device for testing a memory
- Publication number 20020149975
- Publication date Oct 17, 2002
- Carsten Ohlhoff
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated clock generator, particularly for driving a semiconducto...
- Publication number 20020145926
- Publication date Oct 10, 2002
- Peter Pochmuller
- G11 - INFORMATION STORAGE
Information Patent Application
Test configuration and test method for testing a plurality of integ...
- Publication number 20020089341
- Publication date Jul 11, 2002
- Michael Hubner
- G01 - MEASURING TESTING
Information Patent Application
System for testing fast synchronous digital circuits, particularly...
- Publication number 20020070748
- Publication date Jun 13, 2002
- Wolfgang Ernst
- G01 - MEASURING TESTING
Information Patent Application
Integrated memory and memory configuration with a plurality of memo...
- Publication number 20020034118
- Publication date Mar 21, 2002
- Peter Pochmuller
- G11 - INFORMATION STORAGE
Information Patent Application
Field-effect-controlled transistor and method for fabricating the t...
- Publication number 20020014669
- Publication date Feb 7, 2002
- Dietrich Widmann
- B82 - NANO-TECHNOLOGY
Information Patent Application
Address counter for addressing synchronous high-frequency digital c...
- Publication number 20020012286
- Publication date Jan 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing fast synchronous semiconductor circuits
- Publication number 20020012283
- Publication date Jan 31, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing fast integrated digital circuits, in particular...
- Publication number 20020010877
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for generating digital signal patterns
- Publication number 20020009007
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G01 - MEASURING TESTING
Information Patent Application
Circuit configuration for generating control signals for testing hi...
- Publication number 20020010878
- Publication date Jan 24, 2002
- Wolfgang Ernst
- G11 - INFORMATION STORAGE
Information Patent Application
Method and configuration for compensating for parasitic current losses
- Publication number 20020006068
- Publication date Jan 17, 2002
- Peter Pochmuller
- G11 - INFORMATION STORAGE
Information Patent Application
Mram configuration
- Publication number 20020001243
- Publication date Jan 3, 2002
- Peter Pochmuller
- G11 - INFORMATION STORAGE

Peter Pochmuller

Person

Patents Grantslast 30 patents

Configuration for the transmission of signals between a data proces...

Method and probe card configuration for testing a plurality of inte...

Integrated memory and method for operating an integrated memory

Test configuration and test method for testing a plurality of integ...

Integrated dynamic memory, and method for operating the integrated...

Testing device for testing a memory

Integrated clock generator, particularly for driving a semiconducto...

Integrated memory and memory configuration with a plurality of memo...

MRAM configuration

Patents Applicationslast 30 patents

Method and probe card configuration for testing a plurality of inte...

Configuration for the transmission of signals between a data proces...

Integrated dynamic memory, and method for operating the integrated...

Method and device for reading and for checking the time position of...

Testing device for testing a memory

Integrated clock generator, particularly for driving a semiconducto...

Test configuration and test method for testing a plurality of integ...

System for testing fast synchronous digital circuits, particularly...

Integrated memory and memory configuration with a plurality of memo...

Field-effect-controlled transistor and method for fabricating the t...

Address counter for addressing synchronous high-frequency digital c...

System for testing fast synchronous semiconductor circuits

System for testing fast integrated digital circuits, in particular...

Method and device for generating digital signal patterns

Circuit configuration for generating control signals for testing hi...

Method and configuration for compensating for parasitic current losses

Mram configuration