Peter R. Harper

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer level optical module
- Patent number 10,993,317
- Issue date Apr 27, 2021
- Apple Inc.
- Yinjuan He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level optical module
- Patent number 10,811,400
- Issue date Oct 20, 2020
- Apple Inc.
- Yinjuan He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced board level reliability for wafer level packages
- Patent number 9,837,368
- Issue date Dec 5, 2017
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level device and method with cantilever pillar structure
- Patent number 9,806,047
- Issue date Oct 31, 2017
- Maxim Integrated Products, Inc.
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package device having passive energy components
- Patent number 9,564,415
- Issue date Feb 7, 2017
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip wafer level package (WLP) optical device
- Patent number 9,322,901
- Issue date Apr 26, 2016
- Maxim Integrated Products, Inc.
- Nicole D. Kerness
- G01 - MEASURING TESTING
Information Patent Grant
Wafer-level passive device integration
- Patent number 9,324,687
- Issue date Apr 26, 2016
- Maxim Integrated Products, Inc.
- Amit S. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die, high current wafer level package
- Patent number 9,230,903
- Issue date Jan 5, 2016
- Maxim Integrated Products, Inc.
- Arkadii V. Samoilov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die, high current wafer level package
- Patent number 9,087,779
- Issue date Jul 21, 2015
- Maxim Integrated Products, Inc.
- Arkadii V. Samoilov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a buffer material and stiffener
- Patent number 8,878,350
- Issue date Nov 4, 2014
- Maxim Integrated Products, Inc.
- Vivek S. Sridharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit package including a direct...
- Patent number 8,828,799
- Issue date Sep 9, 2014
- Texas Instruments Incorporated
- Kenneth Robert Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging with ball grid array having differenti...
- Patent number 8,674,505
- Issue date Mar 18, 2014
- Texas Instruments Incorporated
- Kenneth R. Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package including a direct connect pad, a blind...
- Patent number 8,598,048
- Issue date Dec 3, 2013
- Texas Instruments Incorporated
- Kenneth Robert Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit stacked package precursors and stacked packaged...
- Patent number 8,377,746
- Issue date Feb 19, 2013
- Texas Instruments Incorporated
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BGA package with traces for plating pads under the chip
- Patent number 8,053,349
- Issue date Nov 8, 2011
- Texas Instruments Incorporated
- Kenneth R. Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit stacked package precursors and stacked packaged...
- Patent number 8,049,320
- Issue date Nov 1, 2011
- Texas Instruments Incorporated
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having wafer level chip scale packaging substr...
- Patent number 7,919,860
- Issue date Apr 5, 2011
- Texas Instruments Incorporated
- Rajen M. Murugan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a bond pad and method therefor
- Patent number 7,271,013
- Issue date Sep 18, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Lois E. Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged IC using insulated wire
- Patent number 7,138,328
- Issue date Nov 21, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Susan H. Downey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged integrated circuit having wire bonds and method therefor
- Patent number 7,015,585
- Issue date Mar 21, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Susan H. Downey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inductive device including bond wires
- Patent number 6,998,952
- Issue date Feb 14, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Yaping Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with test pad structure and method of testing
- Patent number 6,937,047
- Issue date Aug 30, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Tu-Anh Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having a bond pad and method therefor
- Patent number 6,921,979
- Issue date Jul 26, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Susan H. Downey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a bond pad and method therefor
- Patent number 6,844,631
- Issue date Jan 18, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Lois E. Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having optimized wire bond positioning
- Patent number 6,812,580
- Issue date Nov 2, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Robert J. Wenzel
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WAFER LEVEL OPTICAL MODULE
- Publication number 20200107436
- Publication date Apr 2, 2020
- Apple Inc.
- Yinjuan He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL OPTICAL MODULE
- Publication number 20200107435
- Publication date Apr 2, 2020
- Apple Inc.
- Yinjuan He
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE
- Publication number 20150325512
- Publication date Nov 12, 2015
- Maxim Integrated Products, Inc.
- Arkadii V. Samoilov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE
- Publication number 20150279799
- Publication date Oct 1, 2015
- Maxim Integrated Products, Inc.
- Karthik Thambidurai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES
- Publication number 20150255413
- Publication date Sep 10, 2015
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A BUFFER MATERIAL AND STIFFENER
- Publication number 20140306337
- Publication date Oct 16, 2014
- Vivek S. Sridharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP WAFER LEVEL PACKAGE (WLP) OPTICAL DEVICE
- Publication number 20140231635
- Publication date Aug 21, 2014
- Maxim Integrated Products, Inc.
- Nicole D. Kerness
- G01 - MEASURING TESTING
Information Patent Application
MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE
- Publication number 20140183747
- Publication date Jul 3, 2014
- Maxim Integrated Products, Inc.
- Arkadii V. Samoilov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE DEVICE HAVING ENHANCED SECU...
- Publication number 20140077355
- Publication date Mar 20, 2014
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE DEVICE HAVING PASSIVE ENERGY COMPONENTS
- Publication number 20140077385
- Publication date Mar 20, 2014
- Maxim Integrated Products, Inc.
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming an Integrated Circuit Package Including a Direct...
- Publication number 20130295722
- Publication date Nov 7, 2013
- Kenneth Robert Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Packaging With Ball Grid Array Having Differenti...
- Publication number 20130175684
- Publication date Jul 11, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Kenneth R. Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE INCLUDING A DIRECT CONNECT PAD, A BLIND...
- Publication number 20130026642
- Publication date Jan 31, 2013
- Kenneth Robert Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP
- Publication number 20120013003
- Publication date Jan 19, 2012
- TEXAS INSTRUMENTS INCORPORATED
- KENNETH R. RHYNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Stacked Package Precursors and Stacked Packaged...
- Publication number 20120015478
- Publication date Jan 19, 2012
- TEXAS INSTRUMENTS INCORPORATED
- PETER R. HARPER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH EMI SHIELD
- Publication number 20100006987
- Publication date Jan 14, 2010
- Rajen Murugan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED INTEGRATED CIRCUIT HAVING CONFORMAL ELECTROMAGNETIC SHIELD...
- Publication number 20090315156
- Publication date Dec 24, 2009
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Inductance Ball Grid Array Device Having Chip Bumps on Substrat...
- Publication number 20090289362
- Publication date Nov 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Kenneth R. Rhyner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STACKED PACKAGE PRECURSORS AND STACKED PACKAGED...
- Publication number 20090206455
- Publication date Aug 20, 2009
- TEXAS INSTRUMENTS INCORPORATED
- PETER R. HARPER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHO...
- Publication number 20090166889
- Publication date Jul 2, 2009
- Rajen Murugan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTENDED PLATING TRACE IN FLIP CHIP SOLDER MASK WINDOW
- Publication number 20090140419
- Publication date Jun 4, 2009
- Kenneth Rhyner
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
BGA Package with Traces for Plating Pads Under the Chip
- Publication number 20090115072
- Publication date May 7, 2009
- TEXAS INSTRUMENTS INCORPORATED
- KENNETH R. RHYNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Having Wafer Level Chip Scale Packaging Substr...
- Publication number 20090057889
- Publication date Mar 5, 2009
- Texas Instruments Inc.
- Rajen M. Murugan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A STUD BUMP OVER PASSIVATION, AND RELATED DEVICE
- Publication number 20090032939
- Publication date Feb 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Peter R. HARPER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Simplified Substrates for Semiconductor Devices in Package-on-Packa...
- Publication number 20080258285
- Publication date Oct 23, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Peter R. Harper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaged integrated circuit having a heat spreader and method therefor
- Publication number 20070031996
- Publication date Feb 8, 2007
- Sheila F. Chopin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power plane design and jumper wire bond for voltage drop minimization
- Publication number 20070029661
- Publication date Feb 8, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Stanley Craig Beddingfield
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Inductive device including bond wires
- Publication number 20050122198
- Publication date Jun 9, 2005
- Yaping Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with test pad structure and method of testing
- Publication number 20050030055
- Publication date Feb 10, 2005
- Tu-Anh Tran
- G01 - MEASURING TESTING
Information Patent Application
Packaged IC using insulated wire
- Publication number 20040217458
- Publication date Nov 4, 2004
- Susan H. Downey
- H01 - BASIC ELECTRIC ELEMENTS

Peter R. Harper

Person

Patents Grantslast 30 patents

Wafer level optical module

Wafer level optical module

Enhanced board level reliability for wafer level packages

Wafer level device and method with cantilever pillar structure

Semiconductor package device having passive energy components

Multichip wafer level package (WLP) optical device

Wafer-level passive device integration

Multi-die, high current wafer level package

Multi-die, high current wafer level package

Semiconductor device having a buffer material and stiffener

Method of forming an integrated circuit package including a direct...

Integrated circuit packaging with ball grid array having differenti...

Integrated circuit package including a direct connect pad, a blind...

Integrated circuit stacked package precursors and stacked packaged...

BGA package with traces for plating pads under the chip

Integrated circuit stacked package precursors and stacked packaged...

Semiconductor device having wafer level chip scale packaging substr...

Semiconductor device having a bond pad and method therefor

Packaged IC using insulated wire

Packaged integrated circuit having wire bonds and method therefor

Inductive device including bond wires

Integrated circuit with test pad structure and method of testing

Semiconductor device having a bond pad and method therefor

Semiconductor device having a bond pad and method therefor

Semiconductor package having optimized wire bond positioning

Patents Applicationslast 30 patents

WAFER LEVEL OPTICAL MODULE

WAFER LEVEL OPTICAL MODULE

MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE

WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE

ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES

SEMICONDUCTOR DEVICE HAVING A BUFFER MATERIAL AND STIFFENER

MULTICHIP WAFER LEVEL PACKAGE (WLP) OPTICAL DEVICE

MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE

THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE DEVICE HAVING ENHANCED SECU...

SEMICONDUCTOR PACKAGE DEVICE HAVING PASSIVE ENERGY COMPONENTS

Method of Forming an Integrated Circuit Package Including a Direct...

Integrated Circuit Packaging With Ball Grid Array Having Differenti...

INTEGRATED CIRCUIT PACKAGE INCLUDING A DIRECT CONNECT PAD, A BLIND...

BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP

Integrated Circuit Stacked Package Precursors and Stacked Packaged...

INTEGRATED CIRCUIT PACKAGE WITH EMI SHIELD

PACKAGED INTEGRATED CIRCUIT HAVING CONFORMAL ELECTROMAGNETIC SHIELD...

Low Inductance Ball Grid Array Device Having Chip Bumps on Substrat...

INTEGRATED CIRCUIT STACKED PACKAGE PRECURSORS AND STACKED PACKAGED...

PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHO...

EXTENDED PLATING TRACE IN FLIP CHIP SOLDER MASK WINDOW

BGA Package with Traces for Plating Pads Under the Chip

Semiconductor Device Having Wafer Level Chip Scale Packaging Substr...

METHOD OF FORMING A STUD BUMP OVER PASSIVATION, AND RELATED DEVICE

Simplified Substrates for Semiconductor Devices in Package-on-Packa...

Packaged integrated circuit having a heat spreader and method therefor

Power plane design and jumper wire bond for voltage drop minimization

Inductive device including bond wires

Integrated circuit with test pad structure and method of testing

Packaged IC using insulated wire