Peter Schroegmeier

Person

Muenchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for writing to a memory
- Patent number 7,969,806
- Issue date Jun 28, 2011
- Qimonda AG
- Luca De Ambroggi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for determining a memory state of a resistive...
- Patent number 7,876,598
- Issue date Jan 25, 2011
- Qimonda AG
- Peter Schroegmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with Resistivity changing memory cells and metho...
- Patent number 7,706,201
- Issue date Apr 27, 2010
- Qimonda AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method of operating an integrated circuit
- Patent number 7,583,546
- Issue date Sep 1, 2009
- Qimonda AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Read latency control circuit
- Patent number 7,404,018
- Issue date Jul 22, 2008
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit arrangement for controlling write access to a se...
- Patent number 7,224,625
- Issue date May 29, 2007
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel-serial converter
- Patent number 7,215,263
- Issue date May 8, 2007
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device for driving a memory cell of a memory module by means of a c...
- Patent number 7,012,843
- Issue date Mar 14, 2006
- Infineon Technologies AG
- Peter Schroegmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Register for the parallel-serial conversion of data
- Patent number 6,948,014
- Issue date Sep 20, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Latency time circuit for an S-DRAM
- Patent number 6,819,624
- Issue date Nov 16, 2004
- Infineon Technologies AG
- Pramod Acharya
- G11 - INFORMATION STORAGE
Information Patent Grant
DDR memory and storage method
- Patent number 6,731,567
- Issue date May 4, 2004
- Infineon Technologies, AG
- Pramod Acharya
- G11 - INFORMATION STORAGE
Information Patent Grant
Control circuit for an S-DRAM
- Patent number 6,717,886
- Issue date Apr 6, 2004
- Infineon Technologies AG
- Acharya Pramod
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a test operating mode and method for test...
- Patent number 6,670,802
- Issue date Dec 30, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having a row access controller for activating and...
- Patent number 6,532,188
- Issue date Mar 11, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND INTEGRATED CIRCUIT FOR DETERMINING THE STATE OF A RESIST...
- Publication number 20090273967
- Publication date Nov 5, 2009
- Qimonda AG
- Peter Schroegmeier
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY
- Publication number 20090268513
- Publication date Oct 29, 2009
- Luca De Ambroggi
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Writing to a Memory
- Publication number 20090268532
- Publication date Oct 29, 2009
- QIMONDA AG
- Luca De Ambroggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Determining a Memory State of a Resistive...
- Publication number 20090219756
- Publication date Sep 3, 2009
- Peter Schroegmeier
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ
- Publication number 20090046499
- Publication date Feb 19, 2009
- QIMONDA AG
- Jan Boris Philipp
- G11 - INFORMATION STORAGE
Information Patent Application
Method of Operating an Integrated Circuit, Integrated Circuit, and...
- Publication number 20090021976
- Publication date Jan 22, 2009
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Emulated Combination Memory Device
- Publication number 20080306723
- Publication date Dec 11, 2008
- Luca De Ambroggi
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and Method of Operating an Integrated Circuit Technical F...
- Publication number 20080304339
- Publication date Dec 11, 2008
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Test apparatus for testing an integrated circuit
- Publication number 20050273678
- Publication date Dec 8, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Read latency control circuit
- Publication number 20050270852
- Publication date Dec 8, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit arrangement for controlling write access to a se...
- Publication number 20050254307
- Publication date Nov 17, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit with parallel-serial converter
- Publication number 20050219084
- Publication date Oct 6, 2005
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Parallel-serial converter
- Publication number 20050216623
- Publication date Sep 29, 2005
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Register for the parallel-serial conversion of data
- Publication number 20030188064
- Publication date Oct 2, 2003
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
LATENCY TIME CIRCUIT FOR AN S-DRAM
- Publication number 20030174550
- Publication date Sep 18, 2003
- Pramod Acharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Control circuit for an S-DRAM
- Publication number 20030161210
- Publication date Aug 28, 2003
- Pramod Acharya
- G11 - INFORMATION STORAGE
Information Patent Application
DDR memory and storage method
- Publication number 20030151971
- Publication date Aug 14, 2003
- Pramod Acharya
- G11 - INFORMATION STORAGE
Information Patent Application
Device for driving a memory cell of a memory module
- Publication number 20030002354
- Publication date Jan 2, 2003
- Peter Schroegmeier
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having a row access controller for activating and...
- Publication number 20020141279
- Publication date Oct 3, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a test operating mode and method for test...
- Publication number 20020133750
- Publication date Sep 19, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE

Peter Schroegmeier

Person

Patents Grantslast 30 patents

Systems and methods for writing to a memory

Apparatus and method for determining a memory state of a resistive...

Integrated circuit with Resistivity changing memory cells and metho...

Apparatus and method of operating an integrated circuit

Read latency control circuit

Method and circuit arrangement for controlling write access to a se...

Parallel-serial converter

Device for driving a memory cell of a memory module by means of a c...

Register for the parallel-serial conversion of data

Latency time circuit for an S-DRAM

DDR memory and storage method

Control circuit for an S-DRAM

Integrated circuit having a test operating mode and method for test...

Integrated memory having a row access controller for activating and...

Patents Applicationslast 30 patents

METHOD AND INTEGRATED CIRCUIT FOR DETERMINING THE STATE OF A RESIST...

MEMORY DEVICE WITH DIFFERENT TYPES OF PHASE CHANGE MEMORY

Systems and Methods for Writing to a Memory

Apparatus and Method for Determining a Memory State of a Resistive...

INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ

Method of Operating an Integrated Circuit, Integrated Circuit, and...

Emulated Combination Memory Device

Apparatus and Method of Operating an Integrated Circuit Technical F...

Test apparatus for testing an integrated circuit

Read latency control circuit

Method and circuit arrangement for controlling write access to a se...

Integrated circuit with parallel-serial converter

Parallel-serial converter

Register for the parallel-serial conversion of data

LATENCY TIME CIRCUIT FOR AN S-DRAM

Control circuit for an S-DRAM

DDR memory and storage method

Device for driving a memory cell of a memory module

Integrated memory having a row access controller for activating and...

Integrated circuit having a test operating mode and method for test...