Peter Suaris

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Camas, WA, US

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Patents Grantslast 30 patents

Information Patent Grant
Memory re-implementation for field programmable gate arrays
- Patent number 7,716,622
- Issue date May 11, 2010
- Peter Ramyalal Suaris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory re-implementation for field programmable gate arrays
- Patent number 7,251,803
- Issue date Jul 31, 2007
- Peter Ramyalal Suaris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming circuits using a cut-based approach
- Patent number 7,203,919
- Issue date Apr 10, 2007
- Peter Suaris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic topology synthesis and optimization
- Patent number 6,223,334
- Issue date Apr 24, 2001
- Mentor Graphics Corporation
- Peter R. Suaris
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY RE-IMPLEMENTATION FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20070245289
- Publication date Oct 18, 2007
- Peter Ramyalal Suaris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retiming circuits using a cut-based approach
- Publication number 20050132316
- Publication date Jun 16, 2005
- Peter Suaris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory re-implementation for field programmable gate arrays
- Publication number 20050093571
- Publication date May 5, 2005
- Mentor Graphics Corporation
- Peter Ramyalal Suaris
- G06 - COMPUTING CALCULATING COUNTING