Peter Verwegen

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Rottenburg, DE

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Patents Grantslast 30 patents

Information Patent Grant
Optimization of integrated circuit physical design
- Patent number 9,536,030
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Niels Fricke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch and clock structures for enabling race-reduced MUX scan and L...
- Patent number 7,560,964
- Issue date Jul 14, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Edge-triggered master + LSSD slave binary latch
- Patent number 7,401,278
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Peter Verwegen
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero volt/zero current fuse arrangement
- Patent number 6,147,546
- Issue date Nov 14, 2000
- International Business Machines Corporation
- Peter Verwegen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZATION OF INTEGRATED CIRCUIT PHYSICAL DESIGN
- Publication number 20150363531
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Niels Fricke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATCH AND CLOCK STRUCTURES FOR ENABLING RACE-REDUCED MUX SCAN AND L...
- Publication number 20080042712
- Publication date Feb 21, 2008
- International Business Machines Corporation
- David E. LACKEY
- G01 - MEASURING TESTING
Information Patent Application
Latch and clock structures for enabling race-reduced MUX scan and L...
- Publication number 20060208783
- Publication date Sep 21, 2006
- IBM Corporation (International Business Machines)
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
EDGE-TRIGGERED MASTER + LSSD SLAVE BINARY LATCH
- Publication number 20050216806
- Publication date Sep 29, 2005
- International Business Machines Corporation
- Peter Verwegen
- H03 - BASIC ELECTRONIC CIRCUITRY