Peter Weitz

Person

Sauerlach, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor component comprising an interposer substrate
- Patent number 8,624,372
- Issue date Jan 7, 2014
- Infineon Technologies AG
- Wolfgang Hetzel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with re-route layer and stacked die assembly
- Patent number 7,948,071
- Issue date May 24, 2011
- Qimonda AG
- Jochen Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with re-route layer and stacked die assembly
- Patent number 7,422,930
- Issue date Sep 9, 2008
- Infineon Technologies AG
- Jochen Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor module having an internal semiconductor chip stack, a...
- Patent number 7,352,057
- Issue date Apr 1, 2008
- Infineon Technologies AG
- Jurgen Grafe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method for reducing the number of addresses of faulty me...
- Patent number 6,910,161
- Issue date Jun 21, 2005
- Infineon Technologies AG
- Justus Kuhn
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for writing to the magnetoresistive memory cells of an integ...
- Patent number 6,897,101
- Issue date May 24, 2005
- Infineon Technologies AG
- Peter Weitz
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with memory cells in a plurality of memory cell b...
- Patent number 6,721,230
- Issue date Apr 13, 2004
- Infineon Technologies AG
- Peter Weitz
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for controlling the word lines of a memory ma...
- Patent number 6,608,796
- Issue date Aug 19, 2003
- Infineon Technologies AG
- Peter Weitz
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit with Re-Route Layer and Stacked Die Assembly
- Publication number 20080203575
- Publication date Aug 28, 2008
- Jochen Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor component comprising an interposer substrate and meth...
- Publication number 20070040261
- Publication date Feb 22, 2007
- Wolfgang Hetzel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor module having an internal semiconductor chip stack, a...
- Publication number 20060091518
- Publication date May 4, 2006
- Jurgen Grafe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with re-route layer and stacked die assembly
- Publication number 20050194674
- Publication date Sep 8, 2005
- Jochen Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contact-connection device for electronic circuit units and producti...
- Publication number 20050014394
- Publication date Jan 20, 2005
- INFINEON TECHNOLOGIES
- Harry Hedler
- G01 - MEASURING TESTING
Information Patent Application
Carrier for receiving and electrically contacting individually sepa...
- Publication number 20040189333
- Publication date Sep 30, 2004
- Stephan Dobritz
- G01 - MEASURING TESTING
Information Patent Application
Method for writing to the magnetoresistive memory cells of an integ...
- Publication number 20040087134
- Publication date May 6, 2004
- Peter Weitz
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory with memory cells in a plurality of memory cell b...
- Publication number 20030039155
- Publication date Feb 27, 2003
- Peter Weitz
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for controlling the word lines of a memory ma...
- Publication number 20020141278
- Publication date Oct 3, 2002
- Peter Weitz
- G11 - INFORMATION STORAGE
Information Patent Application
Device and method for reducing the number of addresses of faulty me...
- Publication number 20020087926
- Publication date Jul 4, 2002
- Justus Kuhn
- G11 - INFORMATION STORAGE

Peter Weitz

Person

Patents Grantslast 30 patents

Semiconductor component comprising an interposer substrate

Integrated circuit with re-route layer and stacked die assembly

Integrated circuit with re-route layer and stacked die assembly

Semiconductor module having an internal semiconductor chip stack, a...

Device and method for reducing the number of addresses of faulty me...

Method for writing to the magnetoresistive memory cells of an integ...

Integrated memory with memory cells in a plurality of memory cell b...

Circuit configuration for controlling the word lines of a memory ma...

Patents Applicationslast 30 patents

Integrated Circuit with Re-Route Layer and Stacked Die Assembly

Semiconductor component comprising an interposer substrate and meth...

Semiconductor module having an internal semiconductor chip stack, a...

Integrated circuit with re-route layer and stacked die assembly

Contact-connection device for electronic circuit units and producti...

Carrier for receiving and electrically contacting individually sepa...

Method for writing to the magnetoresistive memory cells of an integ...

Integrated memory with memory cells in a plurality of memory cell b...

Circuit configuration for controlling the word lines of a memory ma...

Device and method for reducing the number of addresses of faulty me...