Peter Wohl

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple clock and clock cycle selection for x-tolerant logic built...
- Patent number 12,117,488
- Issue date Oct 15, 2024
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Per-shift X-tolerant logic built-in self-test
- Patent number 11,422,186
- Issue date Aug 23, 2022
- Synopsys, Inc.
- John A. Waicukauski
- G01 - MEASURING TESTING
Information Patent Grant
Reducing X-masking effect for linear time compactors
- Patent number 10,908,213
- Issue date Feb 2, 2021
- Synopsys, Inc.
- Emil Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Increasing compression by reducing padding patterns
- Patent number 10,346,557
- Issue date Jul 9, 2019
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnosis and debug with truncated simulation
- Patent number 9,404,972
- Issue date Aug 2, 2016
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Diagnosis and debug using truncated simulation
- Patent number 9,171,123
- Issue date Oct 27, 2015
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level compression through selective reseeding
- Patent number 9,157,961
- Issue date Oct 13, 2015
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Increasing PRPG-based compression by delayed justification
- Patent number 9,152,752
- Issue date Oct 6, 2015
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Fully X-tolerant, very high scan compression scan test systems and...
- Patent number 8,645,780
- Issue date Feb 4, 2014
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
ATPG and compression by using majority gates
- Patent number 8,549,372
- Issue date Oct 1, 2013
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Fully X-tolerant, very high scan compression scan test systems and...
- Patent number 8,464,115
- Issue date Jun 11, 2013
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Increasing PRPG-based compression by delayed justification
- Patent number 8,429,473
- Issue date Apr 23, 2013
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Fully X-tolerant, very high scan compression scan test systems and...
- Patent number 7,979,763
- Issue date Jul 12, 2011
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Increasing scan compression by using X-chains
- Patent number 7,958,472
- Issue date Jun 7, 2011
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Launch-on-shift support for on-chip-clocking
- Patent number 7,882,410
- Issue date Feb 1, 2011
- Synopsys, Inc.
- Timothy N. Ayres
- G01 - MEASURING TESTING
Information Patent Grant
Pipeline of additional storage elements to shift input/output data...
- Patent number 7,823,034
- Issue date Oct 26, 2010
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression circuit and method of design therefor
- Patent number 7,814,444
- Issue date Oct 12, 2010
- Synopsys, Inc.
- Peter Wohl
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deterministic BIST architecture tolerant of uncertain scan chain ou...
- Patent number 7,237,162
- Issue date Jun 26, 2007
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic bist architecture including MISR filter
- Patent number 6,993,694
- Issue date Jan 31, 2006
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for generating an ATPG model of a memory from beh...
- Patent number 6,959,272
- Issue date Oct 25, 2005
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient compression and application of deterministic patterns in...
- Patent number 6,950,974
- Issue date Sep 27, 2005
- Synopsys Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
System and method for time slicing deterministic patterns for resee...
- Patent number 6,807,646
- Issue date Oct 19, 2004
- Synopsys, Inc.
- Thomas W. Williams
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for performing transition fault simulation along...
- Patent number 6,453,437
- Issue date Sep 17, 2002
- Synopsys, Inc.
- Rohit Kapur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for controlling test data volume in deterministic...
- Patent number 6,385,750
- Issue date May 7, 2002
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
System and process of extracting gate-level descriptions from simul...
- Patent number 6,247,165
- Issue date Jun 12, 2001
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automatic generation of gate-level descriptio...
- Patent number 6,148,436
- Issue date Nov 14, 2000
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical fault modeling system and method
- Patent number 5,796,990
- Issue date Aug 18, 1998
- International Business Machines Corporation
- Mark Alan Erle
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit clocking technique and circuit therefor
- Patent number 5,668,492
- Issue date Sep 16, 1997
- International Business Machines Corporation
- Mark Eric Pedersen
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit chip and pass gate logic family therefor
- Patent number 5,508,641
- Issue date Apr 16, 1996
- International Business Machines Corporation
- David P. Appenzeller
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION
- Publication number 20240110973
- Publication date Apr 4, 2024
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CYCLE TEST GENERATION AND SOURCE-BASED SIMULATION
- Publication number 20220335187
- Publication date Oct 20, 2022
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Increasing Compression by Reducing Padding Patterns
- Publication number 20180156869
- Publication date Jun 7, 2018
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSIS AND DEBUG WITH TRUNCATED SIMULATION
- Publication number 20160025810
- Publication date Jan 28, 2016
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION
- Publication number 20150067629
- Publication date Mar 5, 2015
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-Level Compression Through Selective Reseeding
- Publication number 20140281774
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Fully X-Tolerant, Very High Scan Compression Scan Test Systems And...
- Publication number 20130268817
- Publication date Oct 10, 2013
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Increasing PRPG-Based Compression By Delayed Justification
- Publication number 20130232458
- Publication date Sep 5, 2013
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
ATPG AND COMPRESSION BY USING MAJORITY GATES
- Publication number 20130232459
- Publication date Sep 5, 2013
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Fully X-tolerant, Very High Scan Compression Scan Test Systems And...
- Publication number 20110258503
- Publication date Oct 20, 2011
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Increasing PRPG-Based Compression by Delayed Justification
- Publication number 20110231805
- Publication date Sep 22, 2011
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fully X-Tolerant, Very High Scan Compression Scan Test Systems And...
- Publication number 20100100781
- Publication date Apr 22, 2010
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Increasing Scan Compression By Using X-Chains
- Publication number 20100083199
- Publication date Apr 1, 2010
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Launch-On-Shift Support for On-Chip-Clocking
- Publication number 20080320348
- Publication date Dec 25, 2008
- Synopsys, Inc.
- Timothy N. Ayres
- G01 - MEASURING TESTING
Information Patent Application
Pipeline of additional storage elements to shift input/output data...
- Publication number 20080256274
- Publication date Oct 16, 2008
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Application
Scan compression circuit and method of design therefor
- Publication number 20080256497
- Publication date Oct 16, 2008
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR GENERATING AN ATPG MODEL OF A MEMORY FROM BEH...
- Publication number 20040167764
- Publication date Aug 26, 2004
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Multiple clock and clock cycle selection for x-tolerant logic built...

Per-shift X-tolerant logic built-in self-test

Reducing X-masking effect for linear time compactors

Increasing compression by reducing padding patterns

Diagnosis and debug with truncated simulation

Diagnosis and debug using truncated simulation

Two-level compression through selective reseeding

Increasing PRPG-based compression by delayed justification

Fully X-tolerant, very high scan compression scan test systems and...

ATPG and compression by using majority gates

Fully X-tolerant, very high scan compression scan test systems and...

Increasing PRPG-based compression by delayed justification

Fully X-tolerant, very high scan compression scan test systems and...

Increasing scan compression by using X-chains

Launch-on-shift support for on-chip-clocking

Pipeline of additional storage elements to shift input/output data...

Scan compression circuit and method of design therefor

Deterministic BIST architecture tolerant of uncertain scan chain ou...

Deterministic bist architecture including MISR filter

Method and system for generating an ATPG model of a memory from beh...

Efficient compression and application of deterministic patterns in...

System and method for time slicing deterministic patterns for resee...

Method and system for performing transition fault simulation along...

Method and system for controlling test data volume in deterministic...

System and process of extracting gate-level descriptions from simul...

System and method for automatic generation of gate-level descriptio...

Hierarchical fault modeling system and method

Integrated circuit clocking technique and circuit therefor

Integrated circuit chip and pass gate logic family therefor

Patents Applicationslast 30 patents

DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION

MULTI-CYCLE TEST GENERATION AND SOURCE-BASED SIMULATION

Increasing Compression by Reducing Padding Patterns

DIAGNOSIS AND DEBUG WITH TRUNCATED SIMULATION

DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION

Two-Level Compression Through Selective Reseeding

Fully X-Tolerant, Very High Scan Compression Scan Test Systems And...

Increasing PRPG-Based Compression By Delayed Justification

ATPG AND COMPRESSION BY USING MAJORITY GATES

Fully X-tolerant, Very High Scan Compression Scan Test Systems And...

Increasing PRPG-Based Compression by Delayed Justification

Fully X-Tolerant, Very High Scan Compression Scan Test Systems And...

Increasing Scan Compression By Using X-Chains

Launch-On-Shift Support for On-Chip-Clocking

Pipeline of additional storage elements to shift input/output data...

Scan compression circuit and method of design therefor

METHOD AND SYSTEM FOR GENERATING AN ATPG MODEL OF A MEMORY FROM BEH...