Peter Y. Hsu

Person

Freemont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System of lanes of processing units receiving instructions via shar...
- Patent number 8,180,998
- Issue date May 15, 2012
- NVIDIA Corporation
- Monier Maher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing extended precision in SIMD vector arithmetic operations
- Patent number 8,074,058
- Issue date Dec 6, 2011
- MIPS Technologies, Inc.
- Timothy J. van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing extended precision in SIMD vector arithmetic operations
- Patent number 7,546,443
- Issue date Jun 9, 2009
- MIPS Technologies, Inc.
- Timothy J. van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment and ordering of vector elements for single instruction mu...
- Patent number 7,197,625
- Issue date Mar 27, 2007
- MIPS Technologies, Inc.
- Timothy J. van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for providing extended precision in SIMD vector arithmetic o...
- Patent number 7,159,100
- Issue date Jan 2, 2007
- MIPS Technologies, Inc.
- Timothy van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for software management of on-chip cache
- Patent number 6,859,862
- Issue date Feb 22, 2005
- Nintendo Co., Ltd.
- Yu-Chung C. Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loading previously dispatched slots in multiple instruction dispatc...
- Patent number 6,691,221
- Issue date Feb 10, 2004
- MIPS Technologies, Inc.
- Chandra Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for software management of on-chip cache
- Patent number 6,681,296
- Issue date Jan 20, 2004
- Nintendo Co., Ltd.
- Yu-Chung C. Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction entry with target line index calculated using rel...
- Patent number 6,247,124
- Issue date Jun 12, 2001
- MIPS Technologies, Inc.
- Chandra Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Invalidating instructions in fetched instruction blocks upon predic...
- Patent number 5,954,815
- Issue date Sep 21, 1999
- Silicon Graphics, Inc.
- Chandra Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment and ordering of vector elements for single instruction mu...
- Patent number 5,933,650
- Issue date Aug 3, 1999
- MIPS Technologies, Inc.
- Timothy J. van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for providing extended precision in SIMD vector arithmetic o...
- Patent number 5,864,703
- Issue date Jan 26, 1999
- MIPS Technologies, Inc.
- Timothy van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conflict resolution in interleaved memory systems with multiple par...
- Patent number 5,740,402
- Issue date Apr 14, 1998
- Silicon Graphics, Inc.
- Joseph P. Bratt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for preventing multi-level cache system deadlock in a multi-...
- Patent number 5,632,025
- Issue date May 20, 1997
- Silicon Graphics, Inc.
- Joseph P. Bratt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for processing instructions in a computing system
- Patent number 5,604,909
- Issue date Feb 18, 1997
- Silicon Graphics Computer Systems, Inc.
- Chandra Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling split-level caches in a multi-pro...
- Patent number 5,572,704
- Issue date Nov 5, 1996
- Silicon Graphics, Inc.
- Joseph P. Bratt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug mode for a superscalar RISC processor
- Patent number 5,537,538
- Issue date Jul 16, 1996
- Silicon Graphics, Inc.
- Joseph P. Bratt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable page size translation lookaside buffer
- Patent number 5,526,504
- Issue date Jun 11, 1996
- Silicon Graphics, Inc.
- Peter Y. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system including local and global caches for storing floatin...
- Patent number 5,510,934
- Issue date Apr 23, 1996
- Silicon Graphics, Inc.
- John Brennan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Providing Extended Precision in SIMD Vector Arithmetic Operations
- Publication number 20090249039
- Publication date Oct 1, 2009
- MIPS Technologies, Inc.
- Timothy Van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Alignment and ordering of vector elements for single instruction mu...
- Publication number 20070250683
- Publication date Oct 25, 2007
- MIPS Technologies, Inc.
- Timothy J. Van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing extended precision in SIMD vector arithmetic operations
- Publication number 20060129787
- Publication date Jun 15, 2006
- MIPS Technologies, Inc.
- Timothy van Hook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for processing instructions in a computing system
- Publication number 20030033505
- Publication date Feb 13, 2003
- Chandra Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC O...
- Publication number 20020062436
- Publication date May 23, 2002
- TIMOTHY J. VAN HOOK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for software management of on-chip cache
- Publication number 20020062424
- Publication date May 23, 2002
- Nintendo Co., LTD.
- Yu-Chung C. Liao
- G06 - COMPUTING CALCULATING COUNTING

Peter Y. Hsu

Person

Patents Grantslast 30 patents

System of lanes of processing units receiving instructions via shar...

Providing extended precision in SIMD vector arithmetic operations

Providing extended precision in SIMD vector arithmetic operations

Alignment and ordering of vector elements for single instruction mu...

Method for providing extended precision in SIMD vector arithmetic o...

Method and apparatus for software management of on-chip cache

Loading previously dispatched slots in multiple instruction dispatc...

Method and apparatus for software management of on-chip cache

Branch prediction entry with target line index calculated using rel...

Invalidating instructions in fetched instruction blocks upon predic...

Alignment and ordering of vector elements for single instruction mu...

Method for providing extended precision in SIMD vector arithmetic o...

Conflict resolution in interleaved memory systems with multiple par...

Method for preventing multi-level cache system deadlock in a multi-...

Apparatus for processing instructions in a computing system

System and method for controlling split-level caches in a multi-pro...

Debug mode for a superscalar RISC processor

Variable page size translation lookaside buffer

Memory system including local and global caches for storing floatin...

Patents Applicationslast 30 patents

Providing Extended Precision in SIMD Vector Arithmetic Operations

Alignment and ordering of vector elements for single instruction mu...

Providing extended precision in SIMD vector arithmetic operations

Apparatus for processing instructions in a computing system

METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC O...

Method and apparatus for software management of on-chip cache