Pham Giao

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Set dominant latch with soft error resiliency
- Patent number 7,570,080
- Issue date Aug 4, 2009
- Intel Corporation
- Novat Nintunze
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable power gating circuit
- Patent number 7,385,435
- Issue date Jun 10, 2008
- Intel Corporation
- Giao Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multistage clock delay circuit and method
- Patent number 6,928,572
- Issue date Aug 9, 2005
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a multi-purpose domino adder
- Patent number 6,839,729
- Issue date Jan 4, 2005
- Intel Corporation
- Giao N. Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to calculate the difference of two numbers
- Patent number 6,754,688
- Issue date Jun 22, 2004
- Intel Corporation
- Giao Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric differential domino “AND gate”
- Patent number 6,573,755
- Issue date Jun 3, 2003
- Intel Corporation
- Thomas Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pipelined clock distribution for self resetting CMOS circuits
- Patent number 5,764,083
- Issue date Jun 9, 1998
- International Business Machines Corporation
- Bang T. Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SET DOMINANT LATCH WITH SOFT ERROR RESILIENCY
- Publication number 20090085601
- Publication date Apr 2, 2009
- Novat Nintunze
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable power gating circuit
- Publication number 20080001655
- Publication date Jan 3, 2008
- Giao Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for a multi-purpose domino adder
- Publication number 20030084084
- Publication date May 1, 2003
- Giao N. Pham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multistage clock delay circuit and method
- Publication number 20030005345
- Publication date Jan 2, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric differential domino "AND gate"
- Publication number 20030001622
- Publication date Jan 2, 2003
- Thomas Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus to calculate the difference of two numbers
- Publication number 20020138539
- Publication date Sep 26, 2002
- Giao Pham
- G06 - COMPUTING CALCULATING COUNTING