Phanindra K. Mannava

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamically modulating link width
- Patent number 9,794,349
- Issue date Oct 17, 2017
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized ring protocols and techniques
- Patent number 9,392,062
- Issue date Jul 12, 2016
- Intel Corporation
- Meenakshisundaram R. Chinthamani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing packet size in a communication protocol
- Patent number 9,148,485
- Issue date Sep 29, 2015
- Intel Corporation
- Phanindra K. Mannava
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized ring protocols and techniques
- Patent number 8,898,393
- Issue date Nov 25, 2014
- Intel Corporation
- Meenakshisundaram R. Chinthamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for system level initialization by co...
- Patent number 8,606,934
- Issue date Dec 10, 2013
- Intel Corporation
- Mani Ayyar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generating a packet including multiple operation codes
- Patent number 8,473,567
- Issue date Jun 25, 2013
- Intel Corporation
- Phanindra K. Mannava
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized ring protocols and techniques
- Patent number 8,468,309
- Issue date Jun 18, 2013
- Intel Corporation
- Meenakshisundaram R. Chinthamani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methodology and tools for tabled-based protocol specification and m...
- Patent number 8,443,337
- Issue date May 14, 2013
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically modulating link width
- Patent number 8,046,488
- Issue date Oct 25, 2011
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link level retry scheme
- Patent number 7,991,875
- Issue date Aug 2, 2011
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Negotiable exchange of link layer functional parameters in electron...
- Patent number 7,953,902
- Issue date May 31, 2011
- Intel Corporation
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for flexible and negotiable exchange of link laye...
- Patent number 7,937,505
- Issue date May 3, 2011
- Intel Corporation
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a 3-hop cache coherency protocol
- Patent number 7,836,144
- Issue date Nov 16, 2010
- Intel Corporation
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic allocation of home coherency engine tracker resources in li...
- Patent number 7,831,776
- Issue date Nov 9, 2010
- Intel Corporation
- Phanindra K Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for system level initialization
- Patent number 7,738,484
- Issue date Jun 15, 2010
- Intel Corporation
- Mani Ayyar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link power saving state
- Patent number 7,610,500
- Issue date Oct 27, 2009
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Avoiding deadlocks in a multiprocessor system
- Patent number 7,600,080
- Issue date Oct 6, 2009
- Intel Corporation
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic interconnect width reduction to improve interconnect availa...
- Patent number 7,328,368
- Issue date Feb 5, 2008
- Intel Corporation
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retraining derived clock receivers
- Patent number 7,320,094
- Issue date Jan 15, 2008
- Intel Corporation
- Victor W. Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link power saving state
- Patent number 7,313,712
- Issue date Dec 25, 2007
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link level retry scheme
- Patent number 7,016,304
- Issue date Mar 21, 2006
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZED RING PROTOCOLS AND TECHNIQUES
- Publication number 20150207882
- Publication date Jul 23, 2015
- MEENAKSHISUNDARAM R. CHINTHAMANI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY MODULATING LINK WIDTH
- Publication number 20150081921
- Publication date Mar 19, 2015
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTIMIZED RING PROTOCOLS AND TECHNIQUES
- Publication number 20130262781
- Publication date Oct 3, 2013
- MEENAKSHISUNDARAM R. CHINTHAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Packet Size In A Communication Protocol
- Publication number 20130103783
- Publication date Apr 25, 2013
- Phanindra K. Mannava
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTIMIZED RING PROTOCOLS AND TECHNIQUES
- Publication number 20120079210
- Publication date Mar 29, 2012
- Meenakshisundaram R. Chinthamani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Packet Size In A Communication Protocol
- Publication number 20110238778
- Publication date Sep 29, 2011
- Phanindra K. Mannava
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method, System, and Apparatus for System Level Initialization
- Publication number 20090265472
- Publication date Oct 22, 2009
- Mani Ayyar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methodology and tools for table-based protocol specification and mo...
- Publication number 20090235228
- Publication date Sep 17, 2009
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY
- Publication number 20090171647
- Publication date Jul 2, 2009
- Phanindra Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...
- Publication number 20090064179
- Publication date Mar 5, 2009
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...
- Publication number 20090063813
- Publication date Mar 5, 2009
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...
- Publication number 20090055555
- Publication date Feb 26, 2009
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for a 3-hop cache coherency protocol
- Publication number 20080162661
- Publication date Jul 3, 2008
- Intel Corporation
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic allocation of home coherency engine tracker resources in li...
- Publication number 20080091825
- Publication date Apr 17, 2008
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080091963
- Publication date Apr 17, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080075107
- Publication date Mar 27, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080077814
- Publication date Mar 27, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coordination of snoop responses in a multi-processor system
- Publication number 20080005486
- Publication date Jan 3, 2008
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Link level retry scheme
- Publication number 20070130353
- Publication date Jun 7, 2007
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for flexible and negotiable exchange of link laye...
- Publication number 20070088863
- Publication date Apr 19, 2007
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system, and apparatus for system level initialization
- Publication number 20060126656
- Publication date Jun 15, 2006
- Mani Ayyar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamically modulating link width
- Publication number 20060034295
- Publication date Feb 16, 2006
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Link power saving state
- Publication number 20050262368
- Publication date Nov 24, 2005
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic interconnect width reduction to improve interconnect availa...
- Publication number 20050204193
- Publication date Sep 15, 2005
- Phanindra K. Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus of lowering I/O bus power consumption
- Publication number 20050144488
- Publication date Jun 30, 2005
- Victor W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retraining derived clock receivers
- Publication number 20050022100
- Publication date Jan 27, 2005
- Intel Corporation
- Victor W. Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Link level retry scheme
- Publication number 20020172164
- Publication date Nov 21, 2002
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Phanindra K. Mannava

Person

Patents Grantslast 30 patents

Dynamically modulating link width

Optimized ring protocols and techniques

Reducing packet size in a communication protocol

Optimized ring protocols and techniques

Method, system, and apparatus for system level initialization by co...

Generating a packet including multiple operation codes

Optimized ring protocols and techniques

Methodology and tools for tabled-based protocol specification and m...

Dynamically modulating link width

Link level retry scheme

Negotiable exchange of link layer functional parameters in electron...

Method and system for flexible and negotiable exchange of link laye...

System and method for a 3-hop cache coherency protocol

Dynamic allocation of home coherency engine tracker resources in li...

Method, system, and apparatus for system level initialization

Link power saving state

Avoiding deadlocks in a multiprocessor system

Dynamic interconnect width reduction to improve interconnect availa...

Retraining derived clock receivers

Link power saving state

Link level retry scheme

Patents Applicationslast 30 patents

OPTIMIZED RING PROTOCOLS AND TECHNIQUES

DYNAMICALLY MODULATING LINK WIDTH

OPTIMIZED RING PROTOCOLS AND TECHNIQUES

Reducing Packet Size In A Communication Protocol

OPTIMIZED RING PROTOCOLS AND TECHNIQUES

Reducing Packet Size In A Communication Protocol

Method, System, and Apparatus for System Level Initialization

Methodology and tools for table-based protocol specification and mo...

INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY

METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...

METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...

METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYE...

System and method for a 3-hop cache coherency protocol

Dynamic allocation of home coherency engine tracker resources in li...

LINK POWER SAVING STATE

LINK POWER SAVING STATE

LINK POWER SAVING STATE

Coordination of snoop responses in a multi-processor system

Link level retry scheme

Method and system for flexible and negotiable exchange of link laye...

Method, system, and apparatus for system level initialization

Dynamically modulating link width

Link power saving state

Dynamic interconnect width reduction to improve interconnect availa...

Method and apparatus of lowering I/O bus power consumption

Retraining derived clock receivers

Link level retry scheme