Phat Truong

Person

Houston, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of increasing a timing margin for relaying data to a memory...
- Patent number 8,988,967
- Issue date Mar 24, 2015
- Nanya Technology Corp.
- Phat Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory apparatus and signal delay circuit for generating delayed co...
- Patent number 8,861,291
- Issue date Oct 14, 2014
- Nanya Technology Corporation
- Amna Shawwa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of increasing a timing margin for writing data to a memory a...
- Patent number 8,264,907
- Issue date Sep 11, 2012
- Nanya Technology Corp.
- Phat Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for controlling delay stage of off-chip driver
- Patent number 8,098,083
- Issue date Jan 17, 2012
- Nanya Technology Corp.
- Phat Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power synchronous memory command address scheme
- Patent number 7,940,543
- Issue date May 10, 2011
- Nanya Technology Corp.
- Chia-Jen Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
External compensation for input current source
- Patent number 7,911,262
- Issue date Mar 22, 2011
- Nanya Technology Corp.
- Phat Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to reduce variation in CMOS delay
- Patent number 7,834,683
- Issue date Nov 16, 2010
- Nanya Technology Corp.
- Phat Truong
- G05 - CONTROLLING REGULATING
Information Patent Grant
OCD driver slew rate control
- Patent number 7,737,728
- Issue date Jun 15, 2010
- Nanya Technology Corp.
- Phat Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Temperature and supply-voltage sensing circuit
- Patent number 5,694,073
- Issue date Dec 2, 1997
- Texas Instruments Incorporated
- Timothy J. Coots
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory device performance by delayed power-down
- Patent number 5,668,769
- Issue date Sep 16, 1997
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Array-source line, bitline and wordline sequence in flash operations
- Patent number 5,657,268
- Issue date Aug 12, 1997
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with pre-charge circuit and low-voltage operation mode
- Patent number 5,646,887
- Issue date Jul 8, 1997
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault sensing circuit and method
- Patent number 5,636,226
- Issue date Jun 3, 1997
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase procedure
- Patent number 5,636,162
- Issue date Jun 3, 1997
- Texas Instruments Incorporated
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
Column decoder for virtual ground memory array
- Patent number 5,491,658
- Issue date Feb 13, 1996
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for testing power-on-reset circuitry
- Patent number 5,450,417
- Issue date Sep 12, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for detecting and controlling an array source sig...
- Patent number 5,424,992
- Issue date Jun 13, 1995
- Texas Instruments Incorporated, a Delaware corporation
- Tim M. Coffman
- G11 - INFORMATION STORAGE
Information Patent Grant
High-voltage sensor for integrated circuits
- Patent number 5,397,946
- Issue date Mar 14, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Current-sensing power-on reset circuit for integrated circuits
- Patent number 5,396,115
- Issue date Mar 7, 1995
- Texas Instruments Incorporated
- Tim M. Coffman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for detecting column-line shorts in integrated-c...
- Patent number 5,392,248
- Issue date Feb 21, 1995
- Texas Instruments Incorporated
- Phat C. Truong
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented, multiple-decoder memory array and method for programming...
- Patent number 5,313,432
- Issue date May 17, 1994
- Texas Instruments Incorporated
- Sung-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory array wordline driver circuit with voltage trans...
- Patent number 5,287,536
- Issue date Feb 15, 1994
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit internal test mode indicator circuit
- Patent number 5,255,271
- Issue date Oct 19, 1993
- Texas Instruments Incorporated
- David Tatman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common-line connection for integrated memory array
- Patent number 5,197,029
- Issue date Mar 23, 1993
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for discharging a memory array
- Patent number 5,182,726
- Issue date Jan 26, 1993
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Switch for selectively coupling a power supply to a power bus
- Patent number 5,157,280
- Issue date Oct 20, 1992
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining the field position of an integ...
- Patent number 5,151,880
- Issue date Sep 29, 1992
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit fuse-link tester and test method
- Patent number 5,140,554
- Issue date Aug 18, 1992
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
Bias circuitry for nonvolatile memory array
- Patent number 5,132,933
- Issue date Jul 21, 1992
- John F. Schreck
- G11 - INFORMATION STORAGE
Information Patent Grant
PROM speed measuring method
- Patent number 5,022,008
- Issue date Jun 4, 1991
- Texas Instruments Incorporated
- John F. Schreck
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY APPARATUS AND SIGNAL DELAY CIRCUIT FOR GENERATING DELAYED CO...
- Publication number 20140160873
- Publication date Jun 12, 2014
- Amna Shawwa
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR RELAYING DATA TO MEMORY ARRAY
- Publication number 20120307570
- Publication date Dec 6, 2012
- Phat TRUONG
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME
- Publication number 20110176376
- Publication date Jul 21, 2011
- Chia-Jen Chang
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR WRITING DATA TO MEMORY ARRAY
- Publication number 20110085392
- Publication date Apr 14, 2011
- NANYA TECHNOLOGY CORP.
- Phat TRUONG
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR CONTROLLING DELAY STAGE OF OFF-CHIP DRIVER
- Publication number 20100253391
- Publication date Oct 7, 2010
- Phat Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EXTERNAL COMPENSATION FOR INPUT CURRENT SOURCE
- Publication number 20100244940
- Publication date Sep 30, 2010
- Phat Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD TO REDUCE VARIATION IN CMOS DELAY
- Publication number 20090295466
- Publication date Dec 3, 2009
- Phat Truong
- G05 - CONTROLLING REGULATING
Information Patent Application
LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME
- Publication number 20090238014
- Publication date Sep 24, 2009
- Chia-Jen Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple banks read and data compression for back end test
- Publication number 20070226553
- Publication date Sep 27, 2007
- Khaled Fekih-Romdhane
- G11 - INFORMATION STORAGE

Phat Truong

Person

Patents Grantslast 30 patents

Method of increasing a timing margin for relaying data to a memory...

Memory apparatus and signal delay circuit for generating delayed co...

Method of increasing a timing margin for writing data to a memory a...

Apparatus and method for controlling delay stage of off-chip driver

Low power synchronous memory command address scheme

External compensation for input current source

Method to reduce variation in CMOS delay

OCD driver slew rate control

Temperature and supply-voltage sensing circuit

Memory device performance by delayed power-down

Array-source line, bitline and wordline sequence in flash operations

Sense amplifier with pre-charge circuit and low-voltage operation mode

Fault sensing circuit and method

Erase procedure

Column decoder for virtual ground memory array

Circuit for testing power-on-reset circuitry

Method and device for detecting and controlling an array source sig...

High-voltage sensor for integrated circuits

Current-sensing power-on reset circuit for integrated circuits

Circuit and method for detecting column-line shorts in integrated-c...

Segmented, multiple-decoder memory array and method for programming...

Nonvolatile memory array wordline driver circuit with voltage trans...

Integrated circuit internal test mode indicator circuit

Common-line connection for integrated memory array

Circuit and method for discharging a memory array

Switch for selectively coupling a power supply to a power bus

Method and apparatus for determining the field position of an integ...

Integrated circuit fuse-link tester and test method

Bias circuitry for nonvolatile memory array

PROM speed measuring method

Patents Applicationslast 30 patents

MEMORY APPARATUS AND SIGNAL DELAY CIRCUIT FOR GENERATING DELAYED CO...

METHOD FOR RELAYING DATA TO MEMORY ARRAY

LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME

METHOD FOR WRITING DATA TO MEMORY ARRAY

APPARATUS AND METHOD FOR CONTROLLING DELAY STAGE OF OFF-CHIP DRIVER

EXTERNAL COMPENSATION FOR INPUT CURRENT SOURCE

METHOD TO REDUCE VARIATION IN CMOS DELAY

LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME

Multiple banks read and data compression for back end test