Phi Nguyen

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Use of conductive electrolessly deposited etch stop layers, liner l...
- Patent number 7,008,872
- Issue date Mar 7, 2006
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple exposure technique to pattern tight contact geometries
- Patent number 6,968,532
- Issue date Nov 22, 2005
- Intel Corporation
- Swaminathan (Sam) Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Interconnect structures containing conductive electrolessly deposit...
- Patent number 6,958,547
- Issue date Oct 25, 2005
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of via patterning utilizing hard mask and stripping patterni...
- Patent number 6,472,315
- Issue date Oct 29, 2002
- Intel Corporation
- Phi L. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Highly selective etch process for submicron contacts
- Patent number 6,001,699
- Issue date Dec 14, 1999
- Intel Corporation
- Phi L. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of controlling etch bias with a fixed lithography pattern fo...
- Patent number 5,933,759
- Issue date Aug 3, 1999
- Intel Corporation
- Phi L. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch process to produce rounded top corners for sub-micron silicon...
- Patent number 5,843,846
- Issue date Dec 1, 1998
- Intel Corporation
- Phi L. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Multiple exposure technique to pattern tight contact geometries
- Publication number 20050081178
- Publication date Apr 14, 2005
- Swaminathan (Sam) Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Use of conductive electrolessly deposited etch stop layers, liner l...
- Publication number 20030207560
- Publication date Nov 6, 2003
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect structures containing conductive electrolessly deposit...
- Publication number 20030207561
- Publication date Nov 6, 2003
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Unique via patterning scheme which utilizes hard mask cap for low d...
- Publication number 20010016405
- Publication date Aug 23, 2001
- Phi L. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Use of conductive electrolessly deposited etch stop layers, liner l...

Multiple exposure technique to pattern tight contact geometries

Interconnect structures containing conductive electrolessly deposit...

Method of via patterning utilizing hard mask and stripping patterni...

Highly selective etch process for submicron contacts

Method of controlling etch bias with a fixed lithography pattern fo...

Etch process to produce rounded top corners for sub-micron silicon...

Patents Applicationslast 30 patents

Multiple exposure technique to pattern tight contact geometries

Use of conductive electrolessly deposited etch stop layers, liner l...

Interconnect structures containing conductive electrolessly deposit...

Unique via patterning scheme which utilizes hard mask cap for low d...