Philip A. Jeffery

Person

Mesa, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cell structure for bipolar integrated circuits and method
- Patent number 6,841,810
- Issue date Jan 11, 2005
- Semiconductor Components Industries, LLC
- Philip Alan Jeffery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pin programmable reference
- Patent number 6,429,680
- Issue date Aug 6, 2002
- Semiconductor Components Industries LLC
- Philip Alan Jeffery
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic circuit with output high voltage boost and method of using
- Patent number 6,411,129
- Issue date Jun 25, 2002
- Semiconductor Components Industries LLC
- Philip A. Jeffery
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable termination for integrated circuits
- Patent number 6,362,644
- Issue date Mar 26, 2002
- Semiconductor Components Industries LLC
- Philip A. Jeffery
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Retiming method and means
- Patent number 6,181,757
- Issue date Jan 30, 2001
- Motorola Inc.
- Roland Neumann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for synchronizing signals and structures therefor
- Patent number 5,818,890
- Issue date Oct 6, 1998
- Motorola, Inc.
- David K. Ford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low power output gate
- Patent number 5,023,479
- Issue date Jun 11, 1991
- Motorola, Inc.
- Philip A. Jeffery
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output multiplexer having one gate delay
- Patent number 4,486,880
- Issue date Dec 4, 1984
- Motorola, Inc.
- Philip A. Jeffery
- H03 - BASIC ELECTRONIC CIRCUITRY

Philip A. Jeffery

Person

Patents Grantslast 30 patents

Cell structure for bipolar integrated circuits and method

Pin programmable reference

Logic circuit with output high voltage boost and method of using

Programmable termination for integrated circuits

Retiming method and means

Method for synchronizing signals and structures therefor

Low power output gate

Output multiplexer having one gate delay