Philip Clarke

Person

Leatherhead, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Power-aware memory controller circuitry
- Patent number 9,477,586
- Issue date Oct 25, 2016
- Altera Corporation
- Sam Hedinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for memory interface configuration
- Patent number 8,223,584
- Issue date Jul 17, 2012
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Embroidered electrode
- Patent number 8,006,633
- Issue date Aug 30, 2011
- Koninklijke Philips Electronics N.V.
- Genevieve Bennett
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Postamble timing for DDR memories
- Patent number 7,990,783
- Issue date Aug 2, 2011
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,990,786
- Issue date Aug 2, 2011
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,983,094
- Issue date Jul 19, 2011
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
I/O block for high performance memory interfaces
- Patent number 7,928,770
- Issue date Apr 19, 2011
- Altera Corporation
- Andrew Bellis
- G11 - INFORMATION STORAGE
Information Patent Grant
Distribution and synchronization of a divided clock signal
- Patent number 7,898,296
- Issue date Mar 1, 2011
- Altera Corporation
- Ning Xue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Postamble timing for DDR memories
- Patent number 7,876,630
- Issue date Jan 25, 2011
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
DQS re sync calibration
- Patent number 7,791,375
- Issue date Sep 7, 2010
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Read data path
- Patent number 7,688,116
- Issue date Mar 30, 2010
- Altera Corporation
- Philip Wise
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distribution and synchronization of a divided clock signal
- Patent number 7,642,812
- Issue date Jan 5, 2010
- Altera Corporation
- Ning Xue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,593,273
- Issue date Sep 22, 2009
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,590,008
- Issue date Sep 15, 2009
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic control of memory interface timing
- Patent number 7,589,556
- Issue date Sep 15, 2009
- Altera Corporation
- Johnson Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Apparatus for Memory Interface Configuration and Associated Methods
- Publication number 20120281493
- Publication date Nov 8, 2012
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20090296503
- Publication date Dec 3, 2009
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20080291758
- Publication date Nov 27, 2008
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Embroidered electrode
- Publication number 20070028821
- Publication date Feb 8, 2007
- Koninklijke Philips Electronics N.V.
- Genevieve Bennett
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE

Philip Clarke

Person

Patents Grantslast 30 patents

Power-aware memory controller circuitry

Apparatus for memory interface configuration

Embroidered electrode

Postamble timing for DDR memories

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

I/O block for high performance memory interfaces

Distribution and synchronization of a divided clock signal

Postamble timing for DDR memories

DQS re sync calibration

Read data path

Distribution and synchronization of a divided clock signal

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

Dynamic control of memory interface timing

Patents Applicationslast 30 patents

Apparatus for Memory Interface Configuration and Associated Methods

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

Embroidered electrode