Philip D. Costello

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interconnect multiplexers and methods of reducing contention curren...
- Patent number 9,509,307
- Issue date Nov 29, 2016
- Xilinx, Inc.
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of reducing power of a circuit
- Patent number 7,653,891
- Issue date Jan 26, 2010
- Xilinx, Inc.
- Jason H. Anderson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for simulation of negative bias and temperature instability
- Patent number 7,600,204
- Issue date Oct 6, 2009
- Xilinx, Inc.
- Manoj Chirania
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process monitor vehicle
- Patent number 7,518,394
- Issue date Apr 14, 2009
- Xilinx, Inc.
- Manoj Chirania
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data monitoring for single event upset in a programmable logic device
- Patent number 7,283,409
- Issue date Oct 16, 2007
- Xilinx, Inc.
- Martin L. Voogel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable lookup table with dual input and output terminals in R...
- Patent number 7,265,576
- Issue date Sep 4, 2007
- Xilinx, Inc.
- Venu M. Kondapalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic block providing carry chain with programmable in...
- Patent number 7,256,612
- Issue date Aug 14, 2007
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable lookup table with dual input and output terminals in s...
- Patent number 7,215,138
- Issue date May 8, 2007
- Xilinx, Inc.
- Venu M. Kondapalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed configurable transceiver architecture
- Patent number 7,187,709
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Suresh M. Menon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of measuring performance of a semiconductor device and circu...
- Patent number 7,119,570
- Issue date Oct 10, 2006
- Xilinx, Inc.
- Manoj Chirania
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for voltage regulation within an integrated ci...
- Patent number 7,109,783
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Venu M. Kondapalli
- G05 - CONTROLLING REGULATING
Information Patent Grant
Data monitoring for single event upset in a programmable logic device
- Patent number 7,109,746
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Martin L. Voogel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable circuit optionally configurable as a lookup table or a...
- Patent number 7,075,333
- Issue date Jul 11, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low jitter clock for a physical media access sublayer on a field pr...
- Patent number 6,911,842
- Issue date Jun 28, 2005
- Xilinx, Inc.
- Atul V. Ghia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset in SRAM cells in FPGAs with leaky gate transistors
- Patent number 6,822,894
- Issue date Nov 23, 2004
- Xilinx, Inc.
- Philip D. Costello
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for voltage regulation within an integrated ci...
- Patent number 6,753,722
- Issue date Jun 22, 2004
- Xilinx, Inc.
- Venu M. Kondapalli
- G05 - CONTROLLING REGULATING
Information Patent Grant
High speed bus with tree structure for selecting bus driver
- Patent number 5,936,424
- Issue date Aug 10, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write-assisted memory cell and method of operating same
- Patent number 5,764,564
- Issue date Jun 9, 1998
- Xilinx, Inc.
- Scott O. Frake
- G11 - INFORMATION STORAGE

Philip D. Costello

Person

Patents Grantslast 30 patents

Interconnect multiplexers and methods of reducing contention curren...

Method of reducing power of a circuit

Method for simulation of negative bias and temperature instability

Process monitor vehicle

Data monitoring for single event upset in a programmable logic device

Programmable lookup table with dual input and output terminals in R...

Programmable logic block providing carry chain with programmable in...

Programmable lookup table with dual input and output terminals in s...

High speed configurable transceiver architecture

Method of measuring performance of a semiconductor device and circu...

Method and apparatus for voltage regulation within an integrated ci...

Data monitoring for single event upset in a programmable logic device

Programmable circuit optionally configurable as a lookup table or a...

Low jitter clock for a physical media access sublayer on a field pr...

Single event upset in SRAM cells in FPGAs with leaky gate transistors

Method and apparatus for voltage regulation within an integrated ci...

High speed bus with tree structure for selecting bus driver

Write-assisted memory cell and method of operating same