Philip Pan

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scaleable look-up table based memory
- Patent number 9,548,103
- Issue date Jan 17, 2017
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable high-speed I/O interface
- Patent number 9,473,145
- Issue date Oct 18, 2016
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple data rate interface architecture
- Patent number 9,166,589
- Issue date Oct 20, 2015
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scaleable look-up table based memory
- Patent number 9,123,437
- Issue date Sep 1, 2015
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable high-speed I/O interface
- Patent number 8,829,948
- Issue date Sep 9, 2014
- Altera Corporation
- Bonnie I. Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus to minimize clock tree skew in ICs
- Patent number 8,819,607
- Issue date Aug 26, 2014
- Altera Corporation
- Philip Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaleable look-up table based memory
- Patent number 8,644,100
- Issue date Feb 4, 2014
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance memory interface circuit architecture
- Patent number 8,593,195
- Issue date Nov 26, 2013
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,575,957
- Issue date Nov 5, 2013
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable high-speed interface
- Patent number 8,487,665
- Issue date Jul 16, 2013
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 8,305,121
- Issue date Nov 6, 2012
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,098,082
- Issue date Jan 17, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scaleable look-up table based memory
- Patent number 8,064,280
- Issue date Nov 22, 2011
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,969,215
- Issue date Jun 28, 2011
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 7,859,304
- Issue date Dec 28, 2010
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for the arithmetic over-ride of look up table...
- Patent number 7,812,633
- Issue date Oct 12, 2010
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Look-up table based memory
- Patent number 7,768,430
- Issue date Aug 3, 2010
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-compensating delay chain for multiple-date-rate interfaces
- Patent number 7,725,755
- Issue date May 25, 2010
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 7,710,149
- Issue date May 4, 2010
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed memory in field-programmable gate array integrated circ...
- Patent number 7,656,191
- Issue date Feb 2, 2010
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable high-speed interface
- Patent number 7,586,341
- Issue date Sep 8, 2009
- Altera Corporation
- Bonnie L. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,535,275
- Issue date May 19, 2009
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuitry with data validation
- Patent number 7,487,415
- Issue date Feb 3, 2009
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 7,477,074
- Issue date Jan 13, 2009
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementation of double data rate embedded memory in programmable...
- Patent number 7,460,431
- Issue date Dec 2, 2008
- Altera Corporation
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 7,425,844
- Issue date Sep 16, 2008
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed memory in field-programmable gate array integrated circ...
- Patent number 7,391,236
- Issue date Jun 24, 2008
- Altera Corporation
- David Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for providing redundancy in integrated circuits
- Patent number 7,321,518
- Issue date Jan 22, 2008
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable high speed interface
- Patent number 7,315,188
- Issue date Jan 1, 2008
- Altera Corporation
- Bonnie L. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Control circuit for self-compensating delay chain for multiple-data...
- Patent number 7,231,536
- Issue date Jun 12, 2007
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Programmable High-Speed I/O Interface
- Publication number 20170005662
- Publication date Jan 5, 2017
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable High-Speed I/O Interface
- Publication number 20170005661
- Publication date Jan 5, 2017
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED I/O INTERFACE
- Publication number 20140340125
- Publication date Nov 20, 2014
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20140049287
- Publication date Feb 20, 2014
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED I/O INTERFACE
- Publication number 20130278290
- Publication date Oct 24, 2013
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20120146700
- Publication date Jun 14, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCALEABLE LOOK-UP TABLE BASED MEMORY
- Publication number 20120039142
- Publication date Feb 16, 2012
- Philip Pan
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20110227606
- Publication date Sep 22, 2011
- ALTERA CORPORATION
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20100045349
- Publication date Feb 25, 2010
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Distributed memory in field-programmable gate array integrated circ...
- Publication number 20080231316
- Publication date Sep 25, 2008
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE HIGH-SPEED INTERFACE
- Publication number 20080186056
- Publication date Aug 7, 2008
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Distributed memory in field-programmable gate array integrated circ...
- Publication number 20070146178
- Publication date Jun 28, 2007
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable high speed interface
- Publication number 20060220703
- Publication date Oct 5, 2006
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Loop circuitry with low-pass noise filter
- Publication number 20060164139
- Publication date Jul 27, 2006
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Supply voltage detection circuit
- Publication number 20050253626
- Publication date Nov 17, 2005
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable I/O element circuit for high speed logic devices
- Publication number 20050162187
- Publication date Jul 28, 2005
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Programmable high speed I/O interface
- Publication number 20050134332
- Publication date Jun 23, 2005
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable high speed I/O interface
- Publication number 20030042941
- Publication date Mar 6, 2003
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Scaleable look-up table based memory

Programmable high-speed I/O interface

Multiple data rate interface architecture

Scaleable look-up table based memory

Programmable high-speed I/O interface

Method and apparatus to minimize clock tree skew in ICs

Scaleable look-up table based memory

High performance memory interface circuit architecture

Multiple data rate interface architecture

Programmable high-speed interface

High-performance memory interface circuit architecture

Multiple data rate interface architecture

Scaleable look-up table based memory

High-performance memory interface circuit architecture

Multiple data rate interface architecture

Apparatus and method for the arithmetic over-ride of look up table...

Look-up table based memory

Self-compensating delay chain for multiple-date-rate interfaces

Input buffer for multiple differential I/O standards

Distributed memory in field-programmable gate array integrated circ...

Programmable high-speed interface

High-performance memory interface circuit architecture

Memory circuitry with data validation

Multiple data rate interface architecture

Implementation of double data rate embedded memory in programmable...

Input buffer for multiple differential I/O standards

Distributed memory in field-programmable gate array integrated circ...

Apparatus and methods for providing redundancy in integrated circuits

Programmable high speed interface

Control circuit for self-compensating delay chain for multiple-data...

Patents Applicationslast 30 patents

Programmable High-Speed I/O Interface

Programmable High-Speed I/O Interface

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

PROGRAMMABLE HIGH-SPEED I/O INTERFACE

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

SCALEABLE LOOK-UP TABLE BASED MEMORY

PROGRAMMABLE HIGH-SPEED INTERFACE

PROGRAMMABLE HIGH-SPEED INTERFACE

Distributed memory in field-programmable gate array integrated circ...

PROGRAMMABLE HIGH-SPEED INTERFACE

Distributed memory in field-programmable gate array integrated circ...

Programmable high speed interface

Loop circuitry with low-pass noise filter

Supply voltage detection circuit

Programmable I/O element circuit for high speed logic devices

Programmable high speed I/O interface

Programmable high speed I/O interface