Philip R. Germann

Person

Oronoco, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Residual material detection in backdrilled stubs
- Patent number 9,739,825
- Issue date Aug 22, 2017
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Donor cores to improve integrated circuit yield
- Patent number 9,612,988
- Issue date Apr 4, 2017
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Residual material detection in backdrilled stubs
- Patent number 9,488,690
- Issue date Nov 8, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Residual material detection in backdrilled stubs
- Patent number 9,341,670
- Issue date May 17, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Intelligent chip placement within a three-dimensional chip stack
- Patent number 9,312,199
- Issue date Apr 12, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent chip placement within a three-dimensional chip stack
- Patent number 9,281,261
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect solder bumps for die testing
- Patent number 9,207,275
- Issue date Dec 8, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Grant
Continuity check monitoring for microchip exploitation detection
- Patent number 9,003,559
- Issue date Apr 7, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field-effect transistor and method of creating same
- Patent number 8,823,090
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementing selective rework for chip stacks and silicon carrier a...
- Patent number 8,796,578
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Implementing memory interface with configurable bandwidth
- Patent number 8,788,748
- Issue date Jul 22, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing semiconductor signal-capable capacitors with deep tren...
- Patent number 8,642,456
- Issue date Feb 4, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sorting movable memory hierarchies in a computer system
- Patent number 8,639,879
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing selective rework for chip stacks and silicon carrier a...
- Patent number 8,519,304
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Gerald Keith Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Implementing interleaved-dielectric joining of multi-layer laminates
- Patent number 8,491,739
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Philip R. Germann
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Through silicon via direct FET signal gating
- Patent number 8,492,903
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power domain controller with gated through silicon via having FET w...
- Patent number 8,466,024
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal quality monitoring to defeat microchip exploitation
- Patent number 8,332,659
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for multi-level memory architecture with data prioritization
- Patent number 8,255,628
- Issue date Aug 28, 2012
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistance sensing for defeating microchip exploitation
- Patent number 8,214,657
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Doped implant monitoring for microchip tamper detection
- Patent number 8,172,140
- Issue date May 8, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced architectural interconnect options enabled with flipped di...
- Patent number 8,174,103
- Issue date May 8, 2012
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital data architecture employing redundant links in a daisy chai...
- Patent number 8,108,647
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Gerald Keith Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of enhancing on-chip inductance structure utilizing silicon...
- Patent number 8,079,134
- Issue date Dec 20, 2011
- International Business Machines Corporation
- Andrew Benson Maki
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Structure for memory chip for high capacity memory subsystem suppor...
- Patent number 8,037,270
- Issue date Oct 11, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for dual-mode memory chip for high capacity memory subsystem
- Patent number 8,037,258
- Issue date Oct 11, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for memory chip for high capacity memory subsystem suppor...
- Patent number 8,037,272
- Issue date Oct 11, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory subsystem architecture storing interleaved dat...
- Patent number 8,019,949
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for hub for supporting high capacity memory subsystem
- Patent number 7,996,641
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing enhanced wiring capability for electronic laminate pac...
- Patent number 7,954,081
- Issue date May 31, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS
- Publication number 20160320443
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Application
RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS
- Publication number 20150338457
- Publication date Nov 26, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Application
RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS
- Publication number 20150342057
- Publication date Nov 26, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK
- Publication number 20150162250
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK
- Publication number 20150162259
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DONOR CORES TO IMPROVE INTEGRATED CIRCUIT YIELD
- Publication number 20150032933
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT SOLDER BUMPS FOR DIE TESTING
- Publication number 20140167808
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Application
Implementing Semiconductor Signal-Capable Capacitors with Deep Tren...
- Publication number 20130277798
- Publication date Oct 24, 2013
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPLEMENTING MEMORY INTERFACE WITH CONFIGURABLE BANDWIDTH
- Publication number 20130254473
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING SELECTIVE REWORK FOR CHIP STACKS AND SILICON CARRIER A...
- Publication number 20130233832
- Publication date Sep 12, 2013
- International Business Machines Corporation
- Gerald K. Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
IMPLEMENTING INTERLEAVED-DIELECTRIC JOINING OF MULTI-LAYER LAMINATES
- Publication number 20130221068
- Publication date Aug 29, 2013
- International Business Machines Corporation
- Philip R. Germann
- B32 - LAYERED PRODUCTS
Information Patent Application
THROUGH SILICON VIA DIRECT FET SIGNAL GATING
- Publication number 20130001676
- Publication date Jan 3, 2013
- International Business Machines Corporation
- GERALD K. BARTLEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTOR AND METHOD OF CREATING SAME
- Publication number 20120211829
- Publication date Aug 23, 2012
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power Domain Controller With Gated Through Silicon Via Having FET W...
- Publication number 20120146711
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implementing Interleaved-Dielectric Joining of Multi-Layer Laminates
- Publication number 20120061023
- Publication date Mar 15, 2012
- International Business Machines Corporation
- Philip R. Germann
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
IMPLEMENTING SELECTIVE REWORK FOR CHIP STACKS AND SILICON CARRIER A...
- Publication number 20120006803
- Publication date Jan 12, 2012
- International Business Machines Corporation
- Gerald Keith Bartley
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM
- Publication number 20110238879
- Publication date Sep 29, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING AT-SPEED WAFER FINAL TEST (WFT) WITH COMPLETE CHIP COV...
- Publication number 20100271046
- Publication date Oct 28, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G01 - MEASURING TESTING
Information Patent Application
Digital Data Architecture Employing Redundant Links in a Daisy Chai...
- Publication number 20100191894
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Spread Spectrum Controller with Bit Error Rate Feedback
- Publication number 20100061424
- Publication date Mar 11, 2010
- International Business Machines Corporation
- Philip Raymond Germann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHIELDED WIREBOND
- Publication number 20100025864
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Mark J. Bailey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitance-Based Microchip Exploitation Detection
- Publication number 20100026506
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resistance Sensing for Defeating Microchip Exploitation
- Publication number 20100026326
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal Quality Monitoring to Defeat Microchip Exploitation
- Publication number 20100031375
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Doped Implant Monitoring for Microchip Tamper Detection
- Publication number 20100025479
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interdependent Microchip Functionality for Defeating Exploitation A...
- Publication number 20100026337
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via...
- Publication number 20100024202
- Publication date Feb 4, 2010
- Andrew Benson Maki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitance Structures for Defeating Microchip Tampering
- Publication number 20100026313
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION
- Publication number 20100026336
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Continuity Check Monitoring for Microchip Exploitation Detection
- Publication number 20100031376
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING

Philip R. Germann

Person

Patents Grantslast 30 patents

Residual material detection in backdrilled stubs

Donor cores to improve integrated circuit yield

Residual material detection in backdrilled stubs

Residual material detection in backdrilled stubs

Intelligent chip placement within a three-dimensional chip stack

Intelligent chip placement within a three-dimensional chip stack

Interconnect solder bumps for die testing

Continuity check monitoring for microchip exploitation detection

Field-effect transistor and method of creating same

Implementing selective rework for chip stacks and silicon carrier a...

Implementing memory interface with configurable bandwidth

Implementing semiconductor signal-capable capacitors with deep tren...

Sorting movable memory hierarchies in a computer system

Implementing selective rework for chip stacks and silicon carrier a...

Implementing interleaved-dielectric joining of multi-layer laminates

Through silicon via direct FET signal gating

Power domain controller with gated through silicon via having FET w...

Signal quality monitoring to defeat microchip exploitation

Structure for multi-level memory architecture with data prioritization

Resistance sensing for defeating microchip exploitation

Doped implant monitoring for microchip tamper detection

Enhanced architectural interconnect options enabled with flipped di...

Digital data architecture employing redundant links in a daisy chai...

Method of enhancing on-chip inductance structure utilizing silicon...

Structure for memory chip for high capacity memory subsystem suppor...

Structure for dual-mode memory chip for high capacity memory subsystem

Structure for memory chip for high capacity memory subsystem suppor...

High capacity memory subsystem architecture storing interleaved dat...

Structure for hub for supporting high capacity memory subsystem

Implementing enhanced wiring capability for electronic laminate pac...

Patents Applicationslast 30 patents

RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS

RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS

RESIDUAL MATERIAL DETECTION IN BACKDRILLED STUBS

INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK

INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK

DONOR CORES TO IMPROVE INTEGRATED CIRCUIT YIELD

INTERCONNECT SOLDER BUMPS FOR DIE TESTING

Implementing Semiconductor Signal-Capable Capacitors with Deep Tren...

IMPLEMENTING MEMORY INTERFACE WITH CONFIGURABLE BANDWIDTH

IMPLEMENTING SELECTIVE REWORK FOR CHIP STACKS AND SILICON CARRIER A...

IMPLEMENTING INTERLEAVED-DIELECTRIC JOINING OF MULTI-LAYER LAMINATES

THROUGH SILICON VIA DIRECT FET SIGNAL GATING

FIELD-EFFECT TRANSISTOR AND METHOD OF CREATING SAME

Power Domain Controller With Gated Through Silicon Via Having FET W...

Implementing Interleaved-Dielectric Joining of Multi-Layer Laminates

IMPLEMENTING SELECTIVE REWORK FOR CHIP STACKS AND SILICON CARRIER A...

SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM

IMPLEMENTING AT-SPEED WAFER FINAL TEST (WFT) WITH COMPLETE CHIP COV...

Digital Data Architecture Employing Redundant Links in a Daisy Chai...

Spread Spectrum Controller with Bit Error Rate Feedback

SHIELDED WIREBOND

Capacitance-Based Microchip Exploitation Detection

Resistance Sensing for Defeating Microchip Exploitation

Signal Quality Monitoring to Defeat Microchip Exploitation

Doped Implant Monitoring for Microchip Tamper Detection

Interdependent Microchip Functionality for Defeating Exploitation A...

Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via...

Capacitance Structures for Defeating Microchip Tampering

FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION

Continuity Check Monitoring for Microchip Exploitation Detection