Philippe Boucard

Person

Chesnay, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Encoding byte information on a data bus with separate code
- Patent number 11,940,939
- Issue date Mar 26, 2024
- QUALCOMM Incorporated
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent interconnect power reduction using hardware controlled spl...
- Patent number 10,606,339
- Issue date Mar 31, 2020
- QUALCOMM Incorporated
- Christophe Avoinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero-latency network on chip (NoC)
- Patent number 9,882,839
- Issue date Jan 30, 2018
- QUALCOMM Incorporated
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tunneling within a network-on-chip topology
- Patent number 9,608,935
- Issue date Mar 28, 2017
- QUALCOMM Technologies, Inc.
- Philippe Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network on a chip socket protocol
- Patent number 9,471,538
- Issue date Oct 18, 2016
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA engine with STLB prefetch capabilities and tethered prefetching
- Patent number 9,465,749
- Issue date Oct 11, 2016
- QUALCOMM Technologies, Inc.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System translation look-aside buffer integrated in an interconnect
- Patent number 9,396,130
- Issue date Jul 19, 2016
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network on a chip socket protocol
- Patent number 9,225,665
- Issue date Dec 29, 2015
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power disconnect unit for use in data transport topology of network...
- Patent number 9,177,615
- Issue date Nov 3, 2015
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- G11 - INFORMATION STORAGE
Information Patent Grant
System translation look-aside buffer with request-based allocation...
- Patent number 9,141,556
- Issue date Sep 22, 2015
- QUALCOMM Technologies, Inc.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of distributed initiator-local reorder buffers
- Patent number 9,069,912
- Issue date Jun 30, 2015
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero-latency network on chip (NoC)
- Patent number 9,049,124
- Issue date Jun 2, 2015
- QUALCOMM Technologies, Inc.
- Jean-Jacques Lecler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for supporting target-side security in a cache...
- Patent number 8,930,638
- Issue date Jan 6, 2015
- QUALCOMM Technologies, Inc.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link between chips using virtual channels and credit based flow con...
- Patent number 8,824,295
- Issue date Sep 2, 2014
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transport of PCI-ordered traffic over independent networks
- Patent number 8,788,737
- Issue date Jul 22, 2014
- QUALCOMM Technologies, Inc.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System of interconnections for external functional blocks on a chip...
- Patent number 8,645,557
- Issue date Feb 4, 2014
- QUALCOMM Technologies, Inc.
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and device for managing priority during the transmission of...
- Patent number 8,441,931
- Issue date May 14, 2013
- Arteris Inc.
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network on chip (NoC) with QoS features
- Patent number 8,316,171
- Issue date Nov 20, 2012
- Arteris S.A.
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Managing messages transmitted in an interconnect network
- Patent number 8,254,380
- Issue date Aug 28, 2012
- Arteris
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for transmitting a sequence of messages in an int...
- Patent number 8,031,730
- Issue date Oct 4, 2011
- Arteris
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and device for managing priority during the transmission of...
- Patent number 7,769,027
- Issue date Aug 3, 2010
- Arteris
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electronic memory device
- Patent number 7,755,920
- Issue date Jul 13, 2010
- Arteris
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Message switching system
- Patent number 7,639,704
- Issue date Dec 29, 2009
- Arteris
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and device for switching between agents
- Patent number 7,574,629
- Issue date Aug 11, 2009
- Arteris
- César Douady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital delay device, digital oscillator clock signal generator and...
- Patent number 7,148,728
- Issue date Dec 12, 2006
- Arteris
- Luc Montperrus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
HDLC digital data transmission protocol controller
- Patent number 6,516,004
- Issue date Feb 4, 2003
- T. Sqware Inc.
- César Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
ENCODING BYTE INFORMATION ON A DATA BUS
- Publication number 20230281143
- Publication date Sep 7, 2023
- QUALCOMM Incorporated
- Philippe BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING MEMORY TRANSACTIONS
- Publication number 20210382651
- Publication date Dec 9, 2021
- QUALCOMM Incorporated
- Jean-Jacques LECLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coherent Interconnect Power Reduction Using Hardware Controlled Spl...
- Publication number 20180067542
- Publication date Mar 8, 2018
- QUALCOMM Incorporated
- Christophe Avoinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TUNNELING WITHIN A NETWORK-ON-CHIP TOPOLOGY
- Publication number 20160072731
- Publication date Mar 10, 2016
- QUALCOMM TECHNOLOGIES INC.
- Philippe MARTIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ZERO-LATENCY NETWORK ON CHIP (NOC)
- Publication number 20150256486
- Publication date Sep 10, 2015
- QUALCOMM TECHNOLOGIES INC.
- Philippe BOUCARD
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SELECTIVE CHANGE OF PENDING TRANSACTION URGENCY
- Publication number 20150019776
- Publication date Jan 15, 2015
- QUALCOMM TECHNOLOGIES, INC.
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SUPPORTING TARGET-SIDE SECURITY IN A CACHE...
- Publication number 20140149687
- Publication date May 29, 2014
- QUALCOMM TECHNOLOGIES, INC.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON A CHIP SOCKET PROTOCOL
- Publication number 20140086247
- Publication date Mar 27, 2014
- ARTERIS SAS
- PHILIPPE BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON A CHIP SOCKET PROTOCOL
- Publication number 20140086246
- Publication date Mar 27, 2014
- ARTERIS SAS
- PHILIPPE BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM TRANSLATION LOOK-ASIDE BUFFER INTEGRATED IN AN INTERCONNECT
- Publication number 20140052919
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION...
- Publication number 20140052954
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DMA ENGINE WITH STLB PREFETCH CAPABILITIES AND TETHERED PREFETCHING
- Publication number 20140052955
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED REORDER BUFFERS
- Publication number 20130262733
- Publication date Oct 3, 2013
- ARTERIS SAS
- PHILIPPE BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON CHIP (NOC) WITH QOS FEATURES
- Publication number 20130179613
- Publication date Jul 11, 2013
- ARTERIS S.A.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK BETWEEN CHIPS USING VIRTUAL CHANNELS AND CREDIT BASED FLOW CON...
- Publication number 20130170506
- Publication date Jul 4, 2013
- ARTERIS SAS
- PHILIPPE BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSPORT OF PCI-ORDERED TRAFFIC OVER INDEPENDENT NETWORKS
- Publication number 20130166812
- Publication date Jun 27, 2013
- ARTERIS SAS
- PHILIPPE BOUCARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS POWER DISCONNECT
- Publication number 20130009695
- Publication date Jan 10, 2013
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS CLOCK ADAPTER
- Publication number 20130002315
- Publication date Jan 3, 2013
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Probe
- Publication number 20120331034
- Publication date Dec 27, 2012
- Alain Fawaz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access Latency Metering
- Publication number 20120290810
- Publication date Nov 15, 2012
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON CHIP (NOC) WITH QOS FEATURES
- Publication number 20110302345
- Publication date Dec 8, 2011
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero-latency network on chip (NoC)
- Publication number 20110085550
- Publication date Apr 14, 2011
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Device for Managing Priority During the Transmission of...
- Publication number 20100296400
- Publication date Nov 25, 2010
- Arteris
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND DEVICE FOR SWITCHING BETWEEN AGENTS
- Publication number 20100180163
- Publication date Jul 15, 2010
- Cesar Douady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESSAGE SWITCHING SYSTEM
- Publication number 20100122004
- Publication date May 13, 2010
- Arteris
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Electronic memory device
- Publication number 20090080280
- Publication date Mar 26, 2009
- Arteris
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DETERMINING THE PERFORMANCE OF AN ON-CHIP INT...
- Publication number 20080157753
- Publication date Jul 3, 2008
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for managing messages transmitted in an on-chip interconnect...
- Publication number 20080028090
- Publication date Jan 31, 2008
- Sophana Kok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for managing messages transmitted in an interconn...
- Publication number 20070297404
- Publication date Dec 27, 2007
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Message switching system
- Publication number 20070248097
- Publication date Oct 25, 2007
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Philippe Boucard

Person

Patents Grantslast 30 patents

Encoding byte information on a data bus with separate code

Coherent interconnect power reduction using hardware controlled spl...

Zero-latency network on chip (NoC)

Tunneling within a network-on-chip topology

Network on a chip socket protocol

DMA engine with STLB prefetch capabilities and tethered prefetching

System translation look-aside buffer integrated in an interconnect

Network on a chip socket protocol

Power disconnect unit for use in data transport topology of network...

System translation look-aside buffer with request-based allocation...

System and method of distributed initiator-local reorder buffers

Zero-latency network on chip (NoC)

Method and apparatus for supporting target-side security in a cache...

Link between chips using virtual channels and credit based flow con...

Transport of PCI-ordered traffic over independent networks

System of interconnections for external functional blocks on a chip...

Method and device for managing priority during the transmission of...

Network on chip (NoC) with QoS features

Managing messages transmitted in an interconnect network

System and method for transmitting a sequence of messages in an int...

Method and device for managing priority during the transmission of...

Electronic memory device

Message switching system

Method and device for switching between agents

Digital delay device, digital oscillator clock signal generator and...

HDLC digital data transmission protocol controller

Patents Applicationslast 30 patents

ENCODING BYTE INFORMATION ON A DATA BUS

SCHEDULING MEMORY TRANSACTIONS

Coherent Interconnect Power Reduction Using Hardware Controlled Spl...

TUNNELING WITHIN A NETWORK-ON-CHIP TOPOLOGY

ZERO-LATENCY NETWORK ON CHIP (NOC)

SELECTIVE CHANGE OF PENDING TRANSACTION URGENCY

METHOD AND APPARATUS FOR SUPPORTING TARGET-SIDE SECURITY IN A CACHE...

NETWORK ON A CHIP SOCKET PROTOCOL

NETWORK ON A CHIP SOCKET PROTOCOL

SYSTEM TRANSLATION LOOK-ASIDE BUFFER INTEGRATED IN AN INTERCONNECT

SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION...

DMA ENGINE WITH STLB PREFETCH CAPABILITIES AND TETHERED PREFETCHING

DISTRIBUTED REORDER BUFFERS

NETWORK ON CHIP (NOC) WITH QOS FEATURES

LINK BETWEEN CHIPS USING VIRTUAL CHANNELS AND CREDIT BASED FLOW CON...

TRANSPORT OF PCI-ORDERED TRAFFIC OVER INDEPENDENT NETWORKS

ASYNCHRONOUS POWER DISCONNECT

ASYNCHRONOUS CLOCK ADAPTER

Latency Probe

Memory Access Latency Metering

NETWORK ON CHIP (NOC) WITH QOS FEATURES

Zero-latency network on chip (NoC)

Method and Device for Managing Priority During the Transmission of...

METHOD AND DEVICE FOR SWITCHING BETWEEN AGENTS

MESSAGE SWITCHING SYSTEM

Electronic memory device

SYSTEM AND METHOD FOR DETERMINING THE PERFORMANCE OF AN ON-CHIP INT...

System for managing messages transmitted in an on-chip interconnect...

System and method for managing messages transmitted in an interconn...

Message switching system