Philippe Flatresse

Person

Lapierre, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit comprising transistors with different threshold...
- Patent number 9,911,737
- Issue date Mar 6, 2018
- STMicroelectronics S.A.
- Bastien Giraud
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for generating a topography of an FDSOI integrated circuit
- Patent number 9,092,590
- Issue date Jul 28, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Bastien Giraud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor substrate dynamic biasing circuit
- Patent number 8,570,096
- Issue date Oct 29, 2013
- STMicroelectronics S.A.
- Julien Le Coz
- G05 - CONTROLLING REGULATING
Information Patent Grant
Silicon-on-insulator CMOS integrated circuit with multiple threshol...
- Patent number 8,482,070
- Issue date Jul 9, 2013
- STMicroelectronics (Crolles 2)
- Philippe Flatresse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method for power switch monitoring
- Patent number 7,847,623
- Issue date Dec 7, 2010
- STMicroelectronics S.A.
- Nicolas L'Hostis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for adapting the voltage of a MOS transistor bulk
- Patent number 7,622,983
- Issue date Nov 24, 2009
- STMicroelectronics S.A.
- Olivier Thomas
- G05 - CONTROLLING REGULATING
Information Patent Grant
Gated thyristor and related system and method
- Patent number 7,619,863
- Issue date Nov 17, 2009
- STMicroelectronics, S.A.
- Christophe Entringer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device for characterizing a CMOS logic cell to be produc...
- Patent number 6,871,330
- Issue date Mar 22, 2005
- STMicroelectronics S.A.
- Philippe Flatresse
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD...
- Publication number 20150287722
- Publication date Oct 8, 2015
- STMicroelectronics S.A.
- Bastien Giraud
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR GENERATING A TOPOGRAPHY OF AN FDSOI INTEGRATED CIRCUIT
- Publication number 20140173544
- Publication date Jun 19, 2014
- Bastien Giraud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR SUBSTRATE DYNAMIC BIASING CIRCUIT
- Publication number 20120062313
- Publication date Mar 15, 2012
- STMicroelectronics S.A.
- Julien LE COZ
- G05 - CONTROLLING REGULATING
Information Patent Application
DEVICE AND METHOD FOR POWER SWITCH MONITORING
- Publication number 20090009231
- Publication date Jan 8, 2009
- STMicroelectronics S.A.
- Nicolas Lhostis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Gated thyristor and related system and method
- Publication number 20080088993
- Publication date Apr 17, 2008
- STMicroelectronics S.A.
- Christophe Entringer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND DEVICE FOR ADAPTING THE VOLTAGE OF A MOS TRANSISTOR BULK
- Publication number 20070262809
- Publication date Nov 15, 2007
- STMicroelectronics S.A.
- Olivier Thomas
- G05 - CONTROLLING REGULATING
Information Patent Application
Method and device for representing a cell implemented in a partiall...
- Publication number 20060155523
- Publication date Jul 13, 2006
- STMicroelectronics S.A.
- Vincent Liot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and device for characterizing a CMOS logic cell to be produc...
- Publication number 20040054514
- Publication date Mar 18, 2004
- STMicroelectronics S.A.
- Philippe Flatresse
- G06 - COMPUTING CALCULATING COUNTING

Philippe Flatresse

Person

Patents Grantslast 30 patents

Integrated circuit comprising transistors with different threshold...

Method for generating a topography of an FDSOI integrated circuit

Transistor substrate dynamic biasing circuit

Silicon-on-insulator CMOS integrated circuit with multiple threshol...

Device and method for power switch monitoring

Method and device for adapting the voltage of a MOS transistor bulk

Gated thyristor and related system and method

Method and device for characterizing a CMOS logic cell to be produc...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD...

METHOD FOR GENERATING A TOPOGRAPHY OF AN FDSOI INTEGRATED CIRCUIT

TRANSISTOR SUBSTRATE DYNAMIC BIASING CIRCUIT

DEVICE AND METHOD FOR POWER SWITCH MONITORING

Gated thyristor and related system and method

METHOD AND DEVICE FOR ADAPTING THE VOLTAGE OF A MOS TRANSISTOR BULK

Method and device for representing a cell implemented in a partiall...

Method and device for characterizing a CMOS logic cell to be produc...