Philippe Molson

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for performing design for debug via protocol...
- Patent number 10,866,278
- Issue date Dec 15, 2020
- Intel Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for multiple-channel direct memory access
- Patent number 9,684,615
- Issue date Jun 20, 2017
- Altera Corporation
- Harry Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed peripheral component interconnect (PCIe) input-output de...
- Patent number 9,552,323
- Issue date Jan 24, 2017
- Altera Corporation
- Christopher D. Finan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 9,329,847
- Issue date May 3, 2016
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial reconfiguration using configuration transaction layer packets
- Patent number 9,257,987
- Issue date Feb 9, 2016
- Altera Corporation
- Philippe Molson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Modular direct memory access system
- Patent number 9,053,093
- Issue date Jun 9, 2015
- Altera Corporation
- Harry Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP design system level power estimation
- Patent number 8,661,396
- Issue date Feb 25, 2014
- Altera Corporation
- Jordan Plofsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 8,578,356
- Issue date Nov 5, 2013
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP design system level power estimation
- Patent number 8,402,419
- Issue date Mar 19, 2013
- Altera Corporation
- Jordan Plofsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling optimization of aliased pointers for implementation on p...
- Patent number 8,291,396
- Issue date Oct 16, 2012
- Altera Corporation
- David James Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing protected intellectual property
- Patent number 8,200,472
- Issue date Jun 12, 2012
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded logic analyzer functionality for system level environments
- Patent number 7,991,606
- Issue date Aug 2, 2011
- Altera Corporation
- Maria D'Souza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP design system level power estimation
- Patent number 7,882,457
- Issue date Feb 1, 2011
- Altera Corporation
- Jordan Plofsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 7,873,953
- Issue date Jan 18, 2011
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Finite impulse response (FIR) filter compiler for estimating cost o...
- Patent number 7,865,347
- Issue date Jan 4, 2011
- Altera Corporation
- Tony San
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing protected intellectual property
- Patent number 7,676,355
- Issue date Mar 9, 2010
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level simulation models for hardware modules
- Patent number 7,509,246
- Issue date Mar 24, 2009
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Finite impulse response (FIR) filter compiler
- Patent number 7,480,603
- Issue date Jan 20, 2009
- Altera Corporation
- Tony San
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enabling waveform display in a system desi...
- Patent number 7,360,189
- Issue date Apr 15, 2008
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit accurate hardware simulation in system level simulators
- Patent number 7,318,014
- Issue date Jan 8, 2008
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for simulating a hybrid system with registered...
- Patent number 7,181,384
- Issue date Feb 20, 2007
- Altera Corporation
- Adam Schott Riggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP design system level power estimation
- Patent number 7,143,368
- Issue date Nov 28, 2006
- Altera Corporation
- Jordan Plofsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Finite impulse response (FIR) filter compiler
- Patent number 7,110,927
- Issue date Sep 19, 2006
- Altera Corporation
- Tony San
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware opencore evaluation
- Patent number 7,089,173
- Issue date Aug 8, 2006
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaver-deinterleaver megacore
- Patent number 6,634,009
- Issue date Oct 14, 2003
- Altera Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR PERFORMING DESIGN FOR DEBUG VIA PROTOCOL...
- Publication number 20190219635
- Publication date Jul 18, 2019
- Intel Corporation
- Philippe Molson
- G06 - COMPUTING CALCULATING COUNTING

Philippe Molson

Person

Patents Grantslast 30 patents

Methods and apparatus for performing design for debug via protocol...

Apparatus and methods for multiple-channel direct memory access

High-speed peripheral component interconnect (PCIe) input-output de...

High-level language code sequence optimization for implementing pro...

Partial reconfiguration using configuration transaction layer packets

Modular direct memory access system

DSP design system level power estimation

High-level language code sequence optimization for implementing pro...

DSP design system level power estimation

Scheduling optimization of aliased pointers for implementation on p...

Method and apparatus for providing protected intellectual property

Embedded logic analyzer functionality for system level environments

DSP design system level power estimation

High-level language code sequence optimization for implementing pro...

Finite impulse response (FIR) filter compiler for estimating cost o...

Method and apparatus for providing protected intellectual property

System level simulation models for hardware modules

Finite impulse response (FIR) filter compiler

Method and apparatus for enabling waveform display in a system desi...

Bit accurate hardware simulation in system level simulators

Method and apparatus for simulating a hybrid system with registered...

DSP design system level power estimation

Finite impulse response (FIR) filter compiler

Hardware opencore evaluation

Interleaver-deinterleaver megacore

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR PERFORMING DESIGN FOR DEBUG VIA PROTOCOL...