Philippe Sarrazin

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Timing analysis and optimization of asynchronous circuit designs
- Patent number 10,318,691
- Issue date Jun 11, 2019
- Wave Computing, Inc.
- Philippe Francis Sarrazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for repeated block modification for chip routing
- Patent number 8,893,070
- Issue date Nov 18, 2014
- Synopsys, Inc.
- Jacob Avidan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for repeated block modification for chip routing
- Patent number 8,407,650
- Issue date Mar 26, 2013
- Synopsis, Inc.
- Jacob Avidan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TIMING ANALYSIS AND OPTIMIZATION OF ASYNCHRONOUS CIRCUIT DESIGNS
- Publication number 20170371993
- Publication date Dec 28, 2017
- Wave Computing, Inc.
- Philippe Francis Sarrazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR REPEATED BLOCK MODIFICATION FOR CHIP ROUTING
- Publication number 20130227511
- Publication date Aug 29, 2013
- Synopsys, Inc.
- Jacob Avidan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PLACEMENT OF SOFT MACROS
- Publication number 20070245280
- Publication date Oct 18, 2007
- MAGMA DESIGN AUTOMATION, INC.
- Cornells Van Eijk
- G06 - COMPUTING CALCULATING COUNTING