Philippe Schoenborn

Person

San Mateo, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of using automated test equipment to screen for leakage indu...
- Patent number 7,379,836
- Issue date May 27, 2008
- LSI Corporation
- Philippe Schoenborn
- G01 - MEASURING TESTING
Information Patent Grant
Process for removal of photoresist mask used for making vias in low...
- Patent number 7,071,113
- Issue date Jul 4, 2006
- LSI Logic Corporation
- Yong-Bae Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,969,683
- Issue date Nov 29, 2005
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon-doped hard mask and method of passivating structures during...
- Patent number 6,846,569
- Issue date Jan 25, 2005
- LSI Logic Corporation
- John Hu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
High selectivity SiC etch in integrated circuit fabrication
- Patent number 6,743,725
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,713,386
- Issue date Mar 30, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW...
- Patent number 6,673,721
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Yong-Bae Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming local oxidation with sloped silicon recess
- Patent number 6,579,777
- Issue date Jun 17, 2003
- Cypress Semiconductor Corp.
- Ting P. Yen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon-doped hard mask and method of passivating structures during...
- Patent number 6,576,404
- Issue date Jun 10, 2003
- LSI Logic Corporation
- John Hu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of making a sloped sidewall via for integrated circuit struc...
- Patent number 6,559,048
- Issue date May 6, 2003
- LSI Logic Corporation
- Yong-Bae Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned gate
- Patent number 6,506,670
- Issue date Jan 14, 2003
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming metal-filled openings in low dielectric constan...
- Patent number 6,503,840
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming trenches and vias in layers of low dielectric c...
- Patent number 6,350,700
- Issue date Feb 26, 2002
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma initiating assembly
- Patent number 6,062,163
- Issue date May 16, 2000
- LSI Logic Corporation
- Roger Patrick
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for forming photoresist mask over integrated circuit struct...
- Patent number 5,902,704
- Issue date May 11, 1999
- LSI Logic Corporation
- Philippe Schoenborn
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Formation of gradient doped profile region between channel region a...
- Patent number 5,877,530
- Issue date Mar 2, 1999
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making improved MOS structure with hot carrier reduction
- Patent number 5,663,083
- Issue date Sep 2, 1997
- LSI Logic Corporation
- Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for igniting low pressure inductively coupled plasma
- Patent number 5,639,519
- Issue date Jun 17, 1997
- LSI Logic Corporation
- Roger Patrick
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
MOS structure with hot carrier reduction
- Patent number 5,598,021
- Issue date Jan 28, 1997
- LSI Logic Corporation
- Sungki O
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coil configurations for improved uniformity in inductively coupled...
- Patent number 5,578,165
- Issue date Nov 26, 1996
- LSI Logic Corporation
- Roger Patrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Uniform and repeatable plasma processing
- Patent number 5,474,648
- Issue date Dec 12, 1995
- LSI Logic Corporation
- Roger Patrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for igniting low pressure inductively coupled plasma
- Patent number 5,468,296
- Issue date Nov 21, 1995
- LSI Logic Corporation
- Roger Patrick
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Shallow trench etch
- Patent number 5,413,966
- Issue date May 9, 1995
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coil configurations for improved uniformity in inductively coupled...
- Patent number 5,401,350
- Issue date Mar 28, 1995
- LSI Logic Corporation
- Roger Patrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching process control
- Patent number 5,362,356
- Issue date Nov 8, 1994
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench planarization techniques
- Patent number 5,298,110
- Issue date Mar 29, 1994
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench planarization techniques
- Patent number 5,290,396
- Issue date Mar 1, 1994
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anisotropic polysilicon etching process
- Patent number 5,242,536
- Issue date Sep 7, 1993
- LSI Logic Corporation
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a physical structure on an integrated circuit device and de...
- Patent number 5,082,792
- Issue date Jan 21, 1992
- LSI Logic Corporation
- Nicholas F. Pasch
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Method of using automated test equipment to screen for leakage indu...
- Publication number 20070136023
- Publication date Jun 14, 2007
- LSI Logic Corporation
- Philippe Schoenborn
- G01 - MEASURING TESTING
Information Patent Application
Method of preventing resist poisoning in dual damascene structures
- Publication number 20040161927
- Publication date Aug 19, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for removal of photoresist mask used for making vias in low...
- Publication number 20040072440
- Publication date Apr 15, 2004
- Yong-Bae Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon-doped hard mask and method of passivating structures during...
- Publication number 20030203157
- Publication date Oct 30, 2003
- John Hu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Self aligned gate
- Publication number 20020177280
- Publication date Nov 28, 2002
- Philippe Schoenborn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for forming metal-filled openings in low dielectric constan...
- Publication number 20020164877
- Publication date Nov 7, 2002
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon-doped hard mask and method of passivating structures during...
- Publication number 20020074313
- Publication date Jun 20, 2002
- John Hu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Philippe Schoenborn

Person

Patents Grantslast 30 patents

Method of using automated test equipment to screen for leakage indu...

Process for removal of photoresist mask used for making vias in low...

Method of preventing resist poisoning in dual damascene structures

Carbon-doped hard mask and method of passivating structures during...

High selectivity SiC etch in integrated circuit fabrication

Method of preventing resist poisoning in dual damascene structures

PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW...

Method of forming local oxidation with sloped silicon recess

Carbon-doped hard mask and method of passivating structures during...

Method of making a sloped sidewall via for integrated circuit struc...

Self aligned gate

Process for forming metal-filled openings in low dielectric constan...

Process for forming trenches and vias in layers of low dielectric c...

Plasma initiating assembly

Process for forming photoresist mask over integrated circuit struct...

Formation of gradient doped profile region between channel region a...

Process for making improved MOS structure with hot carrier reduction

Method for igniting low pressure inductively coupled plasma

MOS structure with hot carrier reduction

Coil configurations for improved uniformity in inductively coupled...

Uniform and repeatable plasma processing

Apparatus for igniting low pressure inductively coupled plasma

Shallow trench etch

Coil configurations for improved uniformity in inductively coupled...

Plasma etching process control

Trench planarization techniques

Trench planarization techniques

Anisotropic polysilicon etching process

Forming a physical structure on an integrated circuit device and de...

Patents Applicationslast 30 patents

Method of using automated test equipment to screen for leakage indu...

Method of preventing resist poisoning in dual damascene structures

Process for removal of photoresist mask used for making vias in low...

Carbon-doped hard mask and method of passivating structures during...

Self aligned gate

Process for forming metal-filled openings in low dielectric constan...

Carbon-doped hard mask and method of passivating structures during...