Phillip Johnson

Person

Hellertown, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single event upset immune flip-flop utilizing a small-area highly r...
- Patent number 10,819,318
- Issue date Oct 27, 2020
- Microchip Technology Inc.
- Barry Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delaying data signals
- Patent number 8,648,636
- Issue date Feb 11, 2014
- Lattice Semiconductor Corporation
- Phillip Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop circuit with selectable feedback paths
- Patent number 8,531,222
- Issue date Sep 10, 2013
- Lattice Semiconductor Corporation
- Barry Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delaying data signals
- Patent number 8,441,292
- Issue date May 14, 2013
- Lattice Semiconductor Corporation
- Phillip Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared-array multiple-output digital-to-analog converter
- Patent number 8,164,499
- Issue date Apr 24, 2012
- Lattice Semiconductor Corporation
- Richard Booth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Jitter tolerant delay-locked loop circuit
- Patent number 7,620,839
- Issue date Nov 17, 2009
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hysteresis-based processing for applications such as signal bias mo...
- Patent number 7,616,029
- Issue date Nov 10, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock-and-data-recovery system having a multi-phase clock generator...
- Patent number 7,599,457
- Issue date Oct 6, 2009
- Lattice Semiconductor Corporation
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic delay or advance adjustment of oscillating signal phase
- Patent number 7,586,344
- Issue date Sep 8, 2009
- Lattice Semiconductor Corporation
- Richard Booth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable current output and common-mode voltage buffer
- Patent number 7,535,258
- Issue date May 19, 2009
- Lattice Semiconductor Corporation
- Phillip L. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switch sequencing circuit systems and methods
- Patent number 7,521,969
- Issue date Apr 21, 2009
- Lattice Semiconductor Corporation
- Richard Booth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output clock phase-alignment circuit
- Patent number 7,253,674
- Issue date Aug 7, 2007
- Lattice Semicondutor Corporation
- Phillip L. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable current output buffer
- Patent number 7,215,148
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- Phillip L. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Noise-shielding, switch-controlled load circuitry for oscillators a...
- Patent number 7,132,903
- Issue date Nov 7, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation
- Patent number 7,091,763
- Issue date Aug 15, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digitally controlled delay cells
- Patent number 7,009,433
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable lock detector and corrector
- Patent number 6,970,047
- Issue date Nov 29, 2005
- Lattice Semiconductor Corporation
- Phillip Johnson
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS
- Publication number 20140009194
- Publication date Jan 9, 2014
- Lattice Semiconductor Corporation
- Barry Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delaying Data Signals
- Publication number 20130249717
- Publication date Sep 26, 2013
- Lattice Semiconductor Corporation
- Phillip Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Switch sequencing circuit systems and methods
- Publication number 20080024171
- Publication date Jan 31, 2008
- Lattice Semiconductor Corporation
- Richard Booth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Jitter tolerant delay-locked loop circuit
- Publication number 20070136619
- Publication date Jun 14, 2007
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLL with programmable jitter for loopback serdes testing and the like
- Publication number 20070121711
- Publication date May 31, 2007
- Glen E. Offord
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock-and-data-recovery system having a multi-phase clock generator...
- Publication number 20070030936
- Publication date Feb 8, 2007
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digitally controlled delay cells
- Publication number 20040239387
- Publication date Dec 2, 2004
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY

Phillip Johnson

Person

Patents Grantslast 30 patents

Single event upset immune flip-flop utilizing a small-area highly r...

Delaying data signals

Phase locked loop circuit with selectable feedback paths

Delaying data signals

Shared-array multiple-output digital-to-analog converter

Jitter tolerant delay-locked loop circuit

Hysteresis-based processing for applications such as signal bias mo...

Clock-and-data-recovery system having a multi-phase clock generator...

Dynamic delay or advance adjustment of oscillating signal phase

Programmable current output and common-mode voltage buffer

Switch sequencing circuit systems and methods

Output clock phase-alignment circuit

Programmable current output buffer

Noise-shielding, switch-controlled load circuitry for oscillators a...

Clock generation

Digitally controlled delay cells

Programmable lock detector and corrector

Patents Applicationslast 30 patents

PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS

Delaying Data Signals

Switch sequencing circuit systems and methods

Jitter tolerant delay-locked loop circuit

PLL with programmable jitter for loopback serdes testing and the like

Clock-and-data-recovery system having a multi-phase clock generator...

Digitally controlled delay cells