Phillip M. L. Kwong

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method to generate a float voltage potential at output w...
- Patent number 6,647,500
- Issue date Nov 11, 2003
- Intel Corporation
- Phillip M. L. Kwong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for resetting sense circuitry to a known state in a nonvo...
- Patent number 6,115,290
- Issue date Sep 5, 2000
- Intel Corporation
- Phillip M. L. Kwong
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic single bit per cell to multiple bit per cell memory
- Patent number 6,097,637
- Issue date Aug 1, 2000
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined read architecture for memory
- Patent number 5,684,752
- Issue date Nov 4, 1997
- Intel Corporation
- Duane R. Mills
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined read architecture for memory
- Patent number 5,592,435
- Issue date Jan 7, 1997
- Intel Corporation
- Duane R. Mills
- G11 - INFORMATION STORAGE
Information Patent Grant
Write verify schemes for flash memory with multilevel cells
- Patent number 5,539,690
- Issue date Jul 23, 1996
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for verifying the programming of multi-level f...
- Patent number 5,523,972
- Issue date Jun 4, 1996
- Intel Corporation
- Mamun Rashid
- G11 - INFORMATION STORAGE
Information Patent Grant
Gray coding for a multilevel cell memory system
- Patent number 5,450,363
- Issue date Sep 12, 1995
- Intel Corporation
- Mark Christopherson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory with blocked redundant columns and corresponding...
- Patent number 5,347,484
- Issue date Sep 13, 1994
- Intel Corporation
- Phillip M. Kwong
- G11 - INFORMATION STORAGE

Phillip M. L. Kwong

Person

Patents Grantslast 30 patents

System and method to generate a float voltage potential at output w...

Mechanism for resetting sense circuitry to a known state in a nonvo...

Dynamic single bit per cell to multiple bit per cell memory

Pipelined read architecture for memory

Pipelined read architecture for memory

Write verify schemes for flash memory with multilevel cells

Method and apparatus for verifying the programming of multi-level f...

Gray coding for a multilevel cell memory system

Nonvolatile memory with blocked redundant columns and corresponding...