Pia Naoko Sanda

Person

Chappaqqua, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Tunable error resilience computing
- Patent number 8,832,707
- Issue date Sep 9, 2014
- International Business Machines Corporation
- Daniel J. Henderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of soft error resilience
- Patent number 8,555,234
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Robert Brett Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling system-level effects of soft errors
- Patent number 8,091,050
- Issue date Jan 3, 2012
- International Business Machines Corporation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for VLSI system debug and timing analysis
- Patent number 7,114,136
- Issue date Sep 26, 2006
- International Business Machines Corporation
- Harold W. Chase
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for VLSI visualization
- Patent number 6,895,372
- Issue date May 17, 2005
- International Business Machines Corporation
- Daniel R. Knebel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using time resolved light emission from VLSI circuit devices for na...
- Patent number 6,650,768
- Issue date Nov 18, 2003
- International Business Machines Corporation
- Richard James Evans
- G01 - MEASURING TESTING
Information Patent Grant
Method for IC fault analysis using programmable built-in self test...
- Patent number 6,625,769
- Issue date Sep 23, 2003
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Using time resolved light emission from VLSI circuit devices for na...
- Patent number 6,304,668
- Issue date Oct 16, 2001
- International Business Machines Corporation
- Richard James Evans
Information Patent Grant
Method for identifying long paths in integrated circuits
- Patent number 6,125,461
- Issue date Sep 26, 2000
- International Business Machines Corporation
- Leendert Marinus Huisman
- G01 - MEASURING TESTING
Information Patent Grant
System and method for compressing and analyzing time-resolved optic...
- Patent number 6,028,952
- Issue date Feb 22, 2000
- International Business Machines Corporation
- Jeffrey Alan Kash
- G01 - MEASURING TESTING
Information Patent Grant
Geometric autogeneration of"hard"phase-shift designs for VLSI
- Patent number 5,636,131
- Issue date Jun 3, 1997
- International Business Machines Corporation
- Lars W. Liebmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Geometric autogeneration of "hard" phase-shift designs for VLSI
- Patent number 5,537,648
- Issue date Jul 16, 1996
- International Business Machines Corporation
- Lars W. Liebmann
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Tunable Error Resilience Computing
- Publication number 20110154351
- Publication date Jun 23, 2011
- International Business Machines Corporation
- Daniel J. Henderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification of Soft Error Resilience
- Publication number 20110055777
- Publication date Mar 3, 2011
- International Business Machines Corporation
- Robert Brett Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling System-Level Effects of Soft Errors
- Publication number 20100083203
- Publication date Apr 1, 2010
- International Business Machines Corporation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for VLSI system debug and timing analysis
- Publication number 20050262454
- Publication date Nov 24, 2005
- International Business Machines Corporation
- Harold W. Chase
- G06 - COMPUTING CALCULATING COUNTING

Pia Naoko Sanda

Person

Patents Grantslast 30 patents

Tunable error resilience computing

Verification of soft error resilience

Modeling system-level effects of soft errors

Method for VLSI system debug and timing analysis

System and method for VLSI visualization

Using time resolved light emission from VLSI circuit devices for na...

Method for IC fault analysis using programmable built-in self test...

Using time resolved light emission from VLSI circuit devices for na...

Method for identifying long paths in integrated circuits

System and method for compressing and analyzing time-resolved optic...

Geometric autogeneration of"hard"phase-shift designs for VLSI

Geometric autogeneration of "hard" phase-shift designs for VLSI

Patents Applicationslast 30 patents

Tunable Error Resilience Computing

Verification of Soft Error Resilience

Modeling System-Level Effects of Soft Errors

Method for VLSI system debug and timing analysis