Pierre-Emmanuel Julien Marc Gaillardon

Person

Renens, CH

People

Patents Grantslast 30 patents

Information Patent Grant
Boolean logic optimization in majority-inverter graphs
- Patent number 10,380,309
- Issue date Aug 13, 2019
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amarù
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern-based FPGA logic block and clustering algorithm
- Patent number 9,971,862
- Issue date May 15, 2018
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Xifan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for speeding up boolean satisfiability
- Patent number 9,685,959
- Issue date Jun 20, 2017
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amarú
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resistive switching element and use thereof
- Patent number 9,412,940
- Issue date Aug 9, 2016
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance low-power near-Vt resistive memory-based FPGA
- Patent number 9,276,573
- Issue date Mar 1, 2016
- Ecole Polytechnique Federale de Lausanne
- Pierre-Emmanuel Gaillardon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Controllable polarity FET based arithmetic and differential logic
- Patent number 9,130,568
- Issue date Sep 8, 2015
- Ecole Polytechnique Federale de Lausanne (EPFL)
- Luca Gaetano Amaru
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
BOOLEAN LOGIC OPTIMIZATION IN MAJORITY-INVERTER GRAPHS
- Publication number 20160350469
- Publication date Dec 1, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano Amarù
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resistive Switching Element and Use Thereof
- Publication number 20160322101
- Publication date Nov 3, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY
- Publication number 20160077154
- Publication date Mar 17, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano AMARÚ
- G01 - MEASURING TESTING
Information Patent Application
PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM
- Publication number 20160063168
- Publication date Mar 3, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Xifan TANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA
- Publication number 20160028396
- Publication date Jan 28, 2016
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Pierre-Emmanuel Gaillardon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RESISTIVE SWITCHING ELEMENT AND USE THEREOF
- Publication number 20150200363
- Publication date Jul 16, 2015
- Davide Sacchetto
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC
- Publication number 20140043060
- Publication date Feb 13, 2014
- ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
- Luca Gaetano AMARU
- H03 - BASIC ELECTRONIC CIRCUITRY

Pierre-Emmanuel Julien Marc Gaillardon

Person

Patents Grantslast 30 patents

Boolean logic optimization in majority-inverter graphs

Pattern-based FPGA logic block and clustering algorithm

Method for speeding up boolean satisfiability

Resistive switching element and use thereof

High-performance low-power near-Vt resistive memory-based FPGA

Controllable polarity FET based arithmetic and differential logic

Patents Applicationslast 30 patents

BOOLEAN LOGIC OPTIMIZATION IN MAJORITY-INVERTER GRAPHS

Resistive Switching Element and Use Thereof

METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY

PATTERN-BASED FPGA LOGIC BLOCK AND CLUSTERING ALGORITHM

HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA

RESISTIVE SWITCHING ELEMENT AND USE THEREOF

CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC