Pierre Morin

Person

Grenoble, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method of manufacturing a structure having one or several strained...
- Patent number 10,665,497
- Issue date May 26, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Emmanuel Augendre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a device with a tensile-strained NMOS transi...
- Patent number 10,600,786
- Issue date Mar 24, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Sylvain Maitrejean
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phase change memory
- Patent number 10,510,955
- Issue date Dec 17, 2019
- STMicroelectronics (Crolles 2) SAS
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form strained channel in thin box SOI structures by elast...
- Patent number 10,418,488
- Issue date Sep 17, 2019
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phase-change memory
- Patent number 10,403,682
- Issue date Sep 3, 2019
- STMicroelectronics (Crolles 2) SAS
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with fin and related methods
- Patent number 10,177,255
- Issue date Jan 8, 2019
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form localized relaxed substrate by using condensation
- Patent number 10,068,908
- Issue date Sep 4, 2018
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Co-integration of tensile silicon and compressive silicon germanium
- Patent number 9,905,478
- Issue date Feb 27, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including optimized elastic strain buffer
- Patent number 9,859,426
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Nicolas J. Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with fin and related methods
- Patent number 9,806,196
- Issue date Oct 31, 2017
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Insulation wall between transistors on SOI
- Patent number 8,951,885
- Issue date Feb 10, 2015
- STMicroelectronics (Crolles 2) SAS
- David Barge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of threshold voltage instabilities in a MOS transistor
- Patent number 8,283,707
- Issue date Oct 9, 2012
- STMicroelectronics S.A.
- Jorge Regolini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device comprising at least one MOS transistor having...
- Patent number 7,528,030
- Issue date May 5, 2009
- STMicroelectronics (Crolles 2) SAS
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with MOS transistors with an etch-stop layer h...
- Patent number 7,187,038
- Issue date Mar 6, 2007
- STMicroelectronics S.A.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PHASE-CHANGE MEMORY
- Publication number 20180323237
- Publication date Nov 8, 2018
- STMicroelectronics (Crolles 2) SAS
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHASE CHANGE MEMORY
- Publication number 20180301625
- Publication date Oct 18, 2018
- STMicroelectronics (Crolles 2) SAS
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS
- Publication number 20180026136
- Publication date Jan 25, 2018
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING OPTIMIZED ELASTIC STRAIN BUFFER
- Publication number 20180006154
- Publication date Jan 4, 2018
- International Business Machines Corporation
- Nicolas J. Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...
- Publication number 20170345935
- Publication date Nov 30, 2017
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANS...
- Publication number 20170263607
- Publication date Sep 14, 2017
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Sylvain MAITREJEAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
- Publication number 20170221903
- Publication date Aug 3, 2017
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
- Publication number 20170200653
- Publication date Jul 13, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED S...
- Publication number 20170154900
- Publication date Jun 1, 2017
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS
- Publication number 20170012127
- Publication date Jan 12, 2017
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INSULATION WALL BETWEEN TRANSISTORS ON SOI
- Publication number 20130049163
- Publication date Feb 28, 2013
- David Barge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduction of threshold voltage instabilities in a MOS transistor
- Publication number 20070215919
- Publication date Sep 20, 2007
- STMicroelectronics S.A.
- Jorge Regolini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device comprising at least one MOS transistor having...
- Publication number 20070069256
- Publication date Mar 29, 2007
- STMicroelectronics (Crolles 2) SAS
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with MOS transistors with an etch-stop layer h...
- Publication number 20040135234
- Publication date Jul 15, 2004
- STMicroelectronics S.A.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS

Pierre Morin

Person

Patents Grantslast 30 patents

Method of manufacturing a structure having one or several strained...

Method for fabricating a device with a tensile-strained NMOS transi...

Phase change memory

Method to form strained channel in thin box SOI structures by elast...

Phase-change memory

Semiconductor device with fin and related methods

Method to form localized relaxed substrate by using condensation

Co-integration of tensile silicon and compressive silicon germanium

Semiconductor device including optimized elastic strain buffer

Semiconductor device with fin and related methods

Insulation wall between transistors on SOI

Reduction of threshold voltage instabilities in a MOS transistor

Semiconductor device comprising at least one MOS transistor having...

Semiconductor device with MOS transistors with an etch-stop layer h...

Patents Applicationslast 30 patents

PHASE-CHANGE MEMORY

PHASE CHANGE MEMORY

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

SEMICONDUCTOR DEVICE INCLUDING OPTIMIZED ELASTIC STRAIN BUFFER

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...

METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANS...

METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED S...

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

INSULATION WALL BETWEEN TRANSISTORS ON SOI

Reduction of threshold voltage instabilities in a MOS transistor

Semiconductor device comprising at least one MOS transistor having...

Semiconductor device with MOS transistors with an etch-stop layer h...