Pierre Morin

Person

Albany, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor comprising a channel placed under shear strain and fabri...
- Patent number 11,688,811
- Issue date Jun 27, 2023
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Emmanuel Augendre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor comprising a channel placed under shear strain and fabri...
- Patent number 10,978,594
- Issue date Apr 13, 2021
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Emmanuel Augendre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to induce strain in 3-D microfabricated structures
- Patent number 10,483,393
- Issue date Nov 19, 2019
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming strained MOS transistors
- Patent number 10,263,110
- Issue date Apr 16, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with relaxation reduction liner and associated...
- Patent number 10,204,982
- Issue date Feb 12, 2019
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a semiconductor device using spacers for source/dr...
- Patent number 10,205,022
- Issue date Feb 12, 2019
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor-on-insulator (SOI) device and related methods for mak...
- Patent number 10,103,174
- Issue date Oct 16, 2018
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to induce strain in finFET channels from an adjacent region
- Patent number 10,043,805
- Issue date Aug 7, 2018
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated structure having an epitaxial SiGe layer e...
- Patent number 10,032,912
- Issue date Jul 24, 2018
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned silicon germanium FinFET with relaxed channel region
- Patent number 9,917,194
- Issue date Mar 13, 2018
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to induce strain in 3-D microfabricated structures
- Patent number 9,831,342
- Issue date Nov 28, 2017
- STMicroelectronics
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form strained channel in thin box SOI structures by elast...
- Patent number 9,768,299
- Issue date Sep 19, 2017
- STMicroelectronics Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Co-integration of tensile silicon and compressive silicon germanium
- Patent number 9,679,899
- Issue date Jun 13, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form localized relaxed substrate by using condensation
- Patent number 9,660,081
- Issue date May 23, 2017
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer strained channel FinFET
- Patent number 9,660,080
- Issue date May 23, 2017
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Early PTS with buffer for channel doping control
- Patent number 9,647,086
- Issue date May 9, 2017
- GLOBALFOUNDRIES Inc.
- Steven Bentley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device including fin relaxat...
- Patent number 9,620,626
- Issue date Apr 11, 2017
- Soitec
- Frédéric Allibert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated tensile strained silicon NFET and compressive strained s...
- Patent number 9,607,901
- Issue date Mar 28, 2017
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using a sacrificial gate structure to make a metal gate F...
- Patent number 9,548,361
- Issue date Jan 17, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming stressed semiconductor layer
- Patent number 9,543,214
- Issue date Jan 10, 2017
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon carbide static induction transistor and process for making...
- Patent number 9,490,355
- Issue date Nov 8, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with fin and related methods
- Patent number 9,466,718
- Issue date Oct 11, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Uniaxially-strained FD-SOI finFET
- Patent number 9,466,664
- Issue date Oct 11, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced method of introducing a stress in a transistor channel by...
- Patent number 9,431,538
- Issue date Aug 30, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Shay Reboh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to induce strain in finFET channels from an adjacent region
- Patent number 9,406,783
- Issue date Aug 2, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of locally stressing a semiconductor layer
- Patent number 9,331,175
- Issue date May 3, 2016
- STMicroelectronics S.A.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of stressing a semiconductor layer
- Patent number 9,318,372
- Issue date Apr 19, 2016
- STMicroelectronics S.A.
- Olivier Nier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for single fin cuts using selective ion implants
- Patent number 9,287,130
- Issue date Mar 15, 2016
- GLOBALFOUNDRIES Inc.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Insulation wall between transistors on SOI
- Patent number 9,269,768
- Issue date Feb 23, 2016
- STMicroelectronics (Crolles 2) SAS
- David Barge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Uniaxially-strained FD-SOI finFET
- Patent number 9,252,208
- Issue date Feb 2, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRI...
- Publication number 20210104634
- Publication date Apr 8, 2021
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Emmanuel AUGENDRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES
- Publication number 20180069121
- Publication date Mar 8, 2018
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-MANUFACTURING METHOD OF ZONES WITH DIFFERENT UNIAXIAL STRESSES
- Publication number 20170263495
- Publication date Sep 14, 2017
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Emmanuel AUGENDRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STRAINED MOS TRANSISTORS
- Publication number 20170194498
- Publication date Jul 6, 2017
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED SIGE FINFET
- Publication number 20170084733
- Publication date Mar 23, 2017
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
- Publication number 20170062426
- Publication date Mar 2, 2017
- STMicroelectronics, Inc.
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL
- Publication number 20170047425
- Publication date Feb 16, 2017
- GLOBALFOUNDRIES INC.
- Steven BENTLEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FI...
- Publication number 20170005169
- Publication date Jan 5, 2017
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED S...
- Publication number 20160329253
- Publication date Nov 10, 2016
- STMicroelectronics, Inc.
- Qing Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
- Publication number 20160307899
- Publication date Oct 20, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
- Publication number 20160211376
- Publication date Jul 21, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECT-FREE STRAIN RELAXED BUFFER LAYER
- Publication number 20160190304
- Publication date Jun 30, 2016
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRI...
- Publication number 20160181439
- Publication date Jun 23, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Emmanuel AUGENDRE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES
- Publication number 20160172497
- Publication date Jun 16, 2016
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INTRODUCE STRESS IN A CHANNEL OF A TRANSISTOR USING SACRI...
- Publication number 20160149037
- Publication date May 26, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Shay REBOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIAXIALLY-STRAINED FD-SOI FINFET
- Publication number 20160133692
- Publication date May 12, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON CARBIDE STATIC INDUCTION TRANSISTOR AND PROCESS FOR MAKING...
- Publication number 20160133736
- Publication date May 12, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...
- Publication number 20160118497
- Publication date Apr 28, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAK...
- Publication number 20160093639
- Publication date Mar 31, 2016
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DR...
- Publication number 20160064566
- Publication date Mar 3, 2016
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIAXIALLY-STRAINED FD-SOI FINFET
- Publication number 20160035820
- Publication date Feb 4, 2016
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXAT...
- Publication number 20150325686
- Publication date Nov 12, 2015
- STMicroelectronics, Inc.
- Frédéric Allibert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION
- Publication number 20150303282
- Publication date Oct 22, 2015
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS
- Publication number 20150279994
- Publication date Oct 1, 2015
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES
- Publication number 20150255605
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nicolas Loubet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION
- Publication number 20150249153
- Publication date Sep 3, 2015
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...
- Publication number 20150243784
- Publication date Aug 27, 2015
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES
- Publication number 20150140760
- Publication date May 21, 2015
- STMicroelectronics, Inc.
- Nicolas LOUBET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INSULATION WALL BETWEEN TRANSISTORS ON SOI
- Publication number 20150137242
- Publication date May 21, 2015
- STMicroelectronics (Crolles 2) SAS
- DAVID BARGE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STRESSED SEMICONDUCTOR LAYER
- Publication number 20150118805
- Publication date Apr 30, 2015
- STMicroelectronics S.A.
- Denis Rideau
- H01 - BASIC ELECTRIC ELEMENTS

Pierre Morin

Person

Patents Grantslast 30 patents

Transistor comprising a channel placed under shear strain and fabri...

Transistor comprising a channel placed under shear strain and fabri...

Method to induce strain in 3-D microfabricated structures

Method of forming strained MOS transistors

Semiconductor device with relaxation reduction liner and associated...

Method of making a semiconductor device using spacers for source/dr...

Semiconductor-on-insulator (SOI) device and related methods for mak...

Method to induce strain in finFET channels from an adjacent region

Semiconductor integrated structure having an epitaxial SiGe layer e...

Self-aligned silicon germanium FinFET with relaxed channel region

Method to induce strain in 3-D microfabricated structures

Method to form strained channel in thin box SOI structures by elast...

Co-integration of tensile silicon and compressive silicon germanium

Method to form localized relaxed substrate by using condensation

Multi-layer strained channel FinFET

Early PTS with buffer for channel doping control

Method for fabricating a semiconductor device including fin relaxat...

Integrated tensile strained silicon NFET and compressive strained s...

Method of using a sacrificial gate structure to make a metal gate F...

Method of forming stressed semiconductor layer

Silicon carbide static induction transistor and process for making...

Semiconductor device with fin and related methods

Uniaxially-strained FD-SOI finFET

Enhanced method of introducing a stress in a transistor channel by...

Method to induce strain in finFET channels from an adjacent region

Method of locally stressing a semiconductor layer

Method of stressing a semiconductor layer

Method for single fin cuts using selective ion implants

Insulation wall between transistors on SOI

Uniaxially-strained FD-SOI finFET

Patents Applicationslast 30 patents

TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRI...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

CO-MANUFACTURING METHOD OF ZONES WITH DIFFERENT UNIAXIAL STRESSES

METHOD OF FORMING STRAINED MOS TRANSISTORS

SELF-ALIGNED SIGE FINFET

CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL

METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE FI...

INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED S...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

DEFECT-FREE STRAIN RELAXED BUFFER LAYER

TRANSISTOR COMPRISING A CHANNEL PLACED UNDER SHEAR STRAIN AND FABRI...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

METHOD TO INTRODUCE STRESS IN A CHANNEL OF A TRANSISTOR USING SACRI...

UNIAXIALLY-STRAINED FD-SOI FINFET

SILICON CARBIDE STATIC INDUCTION TRANSISTOR AND PROCESS FOR MAKING...

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...

SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAK...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DR...

UNIAXIALLY-STRAINED FD-SOI FINFET

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FIN RELAXAT...

METHOD TO INDUCE STRAIN IN FINFET CHANNELS FROM AN ADJACENT REGION

SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS

METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES

METHOD TO FORM LOCALIZED RELAXED SUBSTRATE BY USING CONDENSATION

METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELAST...

METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES

INSULATION WALL BETWEEN TRANSISTORS ON SOI

METHOD OF FORMING STRESSED SEMICONDUCTOR LAYER