Pietro Piersimoni

Person

Avezzano (AQ), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Chip protection register unlocking
- Patent number 7,145,799
- Issue date Dec 5, 2006
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Write state machine architecture for flash memory internal instruct...
- Patent number 7,136,307
- Issue date Nov 14, 2006
- Micron Technology, Inc.
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Grant
Write state machine architecture for flash memory internal instruct...
- Patent number 7,027,331
- Issue date Apr 11, 2006
- Micron Technology, Inc.
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple partition memory command user interface
- Patent number 7,028,135
- Issue date Apr 11, 2006
- Micron Technology, Inc.
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip protection register unlocking
- Patent number 6,947,323
- Issue date Sep 20, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for making a memory device with plural substrates each havin...
- Patent number 6,879,522
- Issue date Apr 12, 2005
- Micron Technology, Inc.
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Grant
Write state machine architecture for flash memory internal instruct...
- Patent number 6,618,291
- Issue date Sep 9, 2003
- Micron Technology, Inc.
- Pietro Piersimoni
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Chip protection register unlocking
- Publication number 20050237804
- Publication date Oct 27, 2005
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Write state machine architecture for flash memory internal instruct...
- Publication number 20050195655
- Publication date Sep 8, 2005
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Application
Write state machine architecture for flash memory internal instruct...
- Publication number 20050005060
- Publication date Jan 6, 2005
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Application
Chip protection register unlocking
- Publication number 20040151026
- Publication date Aug 5, 2004
- Micron Technology, Inc.
- Giovanni Naso
- G11 - INFORMATION STORAGE
Information Patent Application
Write state machine architecture for flash memory internal instruct...
- Publication number 20040047181
- Publication date Mar 11, 2004
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple partition memory command user interface
- Publication number 20030062938
- Publication date Apr 3, 2003
- Pietro Piersimoni
- G11 - INFORMATION STORAGE
Information Patent Application
Write state machine architecture for flash memory internal instruct...
- Publication number 20020114182
- Publication date Aug 22, 2002
- Pietro Piersimoni
- G11 - INFORMATION STORAGE

Pietro Piersimoni

Person

Patents Grantslast 30 patents

Chip protection register unlocking

Write state machine architecture for flash memory internal instruct...

Write state machine architecture for flash memory internal instruct...

Multiple partition memory command user interface

Chip protection register unlocking

Method for making a memory device with plural substrates each havin...

Write state machine architecture for flash memory internal instruct...

Patents Applicationslast 30 patents

Chip protection register unlocking

Write state machine architecture for flash memory internal instruct...

Write state machine architecture for flash memory internal instruct...

Chip protection register unlocking

Write state machine architecture for flash memory internal instruct...

Multiple partition memory command user interface

Write state machine architecture for flash memory internal instruct...