Pin-Nan Tseng

Person

Taoyuan, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Dual facing BSI image sensors with wafer level stacking
- Patent number 11,894,408
- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solid-state image sensor including modulation layer decreasing peta...
- Patent number 11,710,754
- Issue date Jul 25, 2023
- VISERA TECHNOLOGIES COMPANY LIMIIED
- Yu-Chi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual facing BSI image sensors with wafer level stacking
- Patent number 11,037,978
- Issue date Jun 15, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for hybrid wafer bonding integrated with CMOS processing
- Patent number 10,510,597
- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pin-Nan Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual facing BSI image sensors with wafer level stacking
- Patent number 10,453,889
- Issue date Oct 22, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for hybrid wafer bonding integrated with CMOS processing
- Patent number 9,728,453
- Issue date Aug 8, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pin-Nan Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual facing BSI image sensors with wafer level stacking
- Patent number 9,711,555
- Issue date Jul 18, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer wiring structure having conductive sidewall etch stoppe...
- Patent number 6,448,649
- Issue date Sep 10, 2002
- Taiwan Semiconductor Manufacturing Company
- Chung-Kuang Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout pattern for improved MOS device matching
- Patent number 6,169,314
- Issue date Jan 2, 2001
- Taiwan Semiconductor Manufacturing Company
- Shyh-Chyi Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout pattern for improved MOS device matching
- Patent number 5,952,698
- Issue date Sep 14, 1999
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shyh-Chyi Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective partial curing of spin-on-glass by ultraviolet radiation...
- Patent number 5,866,481
- Issue date Feb 2, 1999
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chia-Shiung Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned tungsen etch back process to minimize seams in tungste...
- Patent number 5,801,096
- Issue date Sep 1, 1998
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chung-Kuang Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a multi-layer wiring structure having conductive s...
- Patent number 5,756,396
- Issue date May 26, 1998
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chung-Kuang Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating double silicide gate electrode structures on...
- Patent number 5,723,893
- Issue date Mar 3, 1998
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Douglas Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Profile improvement of a metal interconnect structure on a tungsten...
- Patent number 5,712,207
- Issue date Jan 27, 1998
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Kuang Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making metal contacts and interconnections concurrently...
- Patent number 5,702,982
- Issue date Dec 30, 1997
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Kuang Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chemical/mechanical planarization (CMP) apparatus and polish method
- Patent number 5,575,706
- Issue date Nov 19, 1996
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chia S. Tsai
- B24 - GRINDING POLISHING
Information Patent Grant
Method of forming a resistor for ESD protection in a self aligned s...
- Patent number 5,547,881
- Issue date Aug 20, 1996
- Taiwan Semiconductor Manufacturing Company Ltd.
- Jau-Jey Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxygen plasma etch process post contact layer etch back
- Patent number 5,521,121
- Issue date May 28, 1996
- Taiwan Semiconductor Manufacturing Company
- Chia S. Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capping free metal silicide integrated process
- Patent number 5,411,907
- Issue date May 2, 1995
- Taiwan Semiconductor Manufacturing Company
- Chue-San Yoo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING
- Publication number 20240178263
- Publication date May 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLID-STATE IMAGE SENSOR
- Publication number 20230268364
- Publication date Aug 24, 2023
- VisEra Technologies Company Limited
- Pin-Chia TSENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLID-STATE IMAGE SENSOR
- Publication number 20220102412
- Publication date Mar 31, 2022
- VisEra Technologies Company Limited
- Yu-Chi CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual Facing BSI Image Sensors With Wafer Level Stacking
- Publication number 20210305292
- Publication date Sep 30, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual Facing BSI Image Sensors with Wafer Level Stacking
- Publication number 20200052014
- Publication date Feb 13, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Hybrid Wafer Bonding Integrated with CMOS Processing
- Publication number 20170338150
- Publication date Nov 23, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pin-Nan Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual Facing BSI Image Sensors with Wafer Level Stacking
- Publication number 20170317118
- Publication date Nov 2, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual Facing BSI Image Sensors with Wafer Level Stacking
- Publication number 20150091124
- Publication date Apr 2, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Hybrid Wafer Bonding Integrated with CMOS Processing
- Publication number 20140273347
- Publication date Sep 18, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pin-Nan Tseng
- H01 - BASIC ELECTRIC ELEMENTS

Pin-Nan Tseng

Person

Patents Grantslast 30 patents

Dual facing BSI image sensors with wafer level stacking

Solid-state image sensor including modulation layer decreasing peta...

Dual facing BSI image sensors with wafer level stacking

Methods for hybrid wafer bonding integrated with CMOS processing

Dual facing BSI image sensors with wafer level stacking

Methods for hybrid wafer bonding integrated with CMOS processing

Dual facing BSI image sensors with wafer level stacking

Multi-layer wiring structure having conductive sidewall etch stoppe...

Layout pattern for improved MOS device matching

Layout pattern for improved MOS device matching

Selective partial curing of spin-on-glass by ultraviolet radiation...

Self-aligned tungsen etch back process to minimize seams in tungste...

Method of making a multi-layer wiring structure having conductive s...

Method for fabricating double silicide gate electrode structures on...

Profile improvement of a metal interconnect structure on a tungsten...

Method for making metal contacts and interconnections concurrently...

Chemical/mechanical planarization (CMP) apparatus and polish method

Method of forming a resistor for ESD protection in a self aligned s...

Oxygen plasma etch process post contact layer etch back

Capping free metal silicide integrated process

Patents Applicationslast 30 patents

DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING

SOLID-STATE IMAGE SENSOR

SOLID-STATE IMAGE SENSOR

Dual Facing BSI Image Sensors With Wafer Level Stacking

Dual Facing BSI Image Sensors with Wafer Level Stacking

Methods for Hybrid Wafer Bonding Integrated with CMOS Processing

Dual Facing BSI Image Sensors with Wafer Level Stacking

Dual Facing BSI Image Sensors with Wafer Level Stacking

Methods for Hybrid Wafer Bonding Integrated with CMOS Processing