Ping JIANG

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low damage low-k dielectric etch
- Patent number 10,453,700
- Issue date Oct 22, 2019
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating semiconductors
- Patent number 9,881,795
- Issue date Jan 30, 2018
- Texas Instruments Incorporated
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor combination stress testing
- Patent number 9,678,132
- Issue date Jun 13, 2017
- Texas Instruments Incorporated
- Andrew Marshall
- G01 - MEASURING TESTING
Information Patent Grant
Method of fabricating semiconductors
- Patent number 9,490,143
- Issue date Nov 8, 2016
- Texas Instruments Incorporated
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for controlling the uniformity of a ballistic ele...
- Patent number 8,083,961
- Issue date Dec 27, 2011
- Tokyo Electron Limited
- Lee Chen
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
Poison-free and low ULK damage integration scheme for damascene int...
- Patent number 8,008,200
- Issue date Aug 30, 2011
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,943,499
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poison-free and low ULK damage integration scheme for damascene int...
- Patent number 7,884,019
- Issue date Feb 8, 2011
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment and repair processes for reducing sidewall damage...
- Patent number 7,741,224
- Issue date Jun 22, 2010
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,312
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,313
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gas switching during an etch process to modulate the characteristic...
- Patent number 7,572,733
- Issue date Aug 11, 2009
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etching systems and processing gas specie modulation
- Patent number 7,560,385
- Issue date Jul 14, 2009
- Texas Instruments Incorporated
- Francis G. Celii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to facilitate etch uniformity and selectivity
- Patent number 7,341,941
- Issue date Mar 11, 2008
- Texas Instruments Incorporated
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device having a silicided...
- Patent number 7,338,888
- Issue date Mar 4, 2008
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gas switching during an etch process to modulate the characteristic...
- Patent number 7,300,878
- Issue date Nov 27, 2007
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma treatment for silicon-based dielectrics
- Patent number 7,282,436
- Issue date Oct 16, 2007
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming single damascene via or trench cavities and for...
- Patent number 7,214,609
- Issue date May 8, 2007
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for using silicided dual work function metal gates
- Patent number 7,183,187
- Issue date Feb 27, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a fully silicided gate electrode and me...
- Patent number 7,148,143
- Issue date Dec 12, 2006
- Texas Instruments Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual cap layer in damascene interconnection processes
- Patent number 7,129,162
- Issue date Oct 31, 2006
- Texas Instruments Incorporated
- Hyesook Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BARC etch comprising a selective etch chemistry and a high polymeri...
- Patent number 6,900,123
- Issue date May 31, 2005
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ plasma ash/treatment after via etch of low-k films for pois...
- Patent number 6,797,633
- Issue date Sep 28, 2004
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to determine a complete etch in integrated devices
- Patent number 6,645,781
- Issue date Nov 11, 2003
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assembly and method for improved scanning electron microscope analy...
- Patent number 6,642,518
- Issue date Nov 4, 2003
- Texas Instruments Incorporated
- Fred Y. Clark
- G01 - MEASURING TESTING
Information Patent Grant
Plasma treatment of low-k dielectric films to improve patterning
- Patent number 6,620,560
- Issue date Sep 16, 2003
- Texax Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defect and etch rate control in trench etch for dual damascene patt...
- Patent number 6,455,411
- Issue date Sep 24, 2002
- Texas Instruments Incorporated
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene cap layer process for integrated circuit interconnects
- Patent number 6,410,426
- Issue date Jun 25, 2002
- Texas Instruments Incorporated
- Guoqiang Xing
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW DAMAGE LOW-K DIELECTRIC ETCH
- Publication number 20170178955
- Publication date Jun 22, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Ping JIANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING SEMICONDUCTORS
- Publication number 20170148634
- Publication date May 25, 2017
- TEXAS INSTRUMENTS INCORPORATED
- David Gerald Farber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR COMBINATION STRESS TESTING
- Publication number 20160061877
- Publication date Mar 3, 2016
- Andrew Marshall
- G01 - MEASURING TESTING
Information Patent Application
POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INT...
- Publication number 20110143533
- Publication date Jun 16, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION
- Publication number 20110034023
- Publication date Feb 10, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI Integration Method Using SOG as a Sacrificial Planarization Layer
- Publication number 20100041231
- Publication date Feb 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER
- Publication number 20090111224
- Publication date Apr 30, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SiC Film for Semiconductor Processing
- Publication number 20090081864
- Publication date Mar 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon Carbide Doped Oxide Hardmask For Single and Dual Damascene...
- Publication number 20090075480
- Publication date Mar 19, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Laura M. Matz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE...
- Publication number 20090017563
- Publication date Jan 15, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INT...
- Publication number 20080305625
- Publication date Dec 11, 2008
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATI...
- Publication number 20080299718
- Publication date Dec 4, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gas switching during an etch process to modulate the characteristic...
- Publication number 20080090423
- Publication date Apr 17, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FAB...
- Publication number 20080057701
- Publication date Mar 6, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Edward Raymond Engbrecht
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for controlling the uniformity of a ballistic ele...
- Publication number 20080023440
- Publication date Jan 31, 2008
- TOKYO ELECTRON LIMITED
- Lee Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GAS SWITCHING DURING AN ETCH PROCESS TO MODULATE THE CHARACTERISTIC...
- Publication number 20070275561
- Publication date Nov 29, 2007
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI integration method using SOG as a sacrificial planarization layer
- Publication number 20070173047
- Publication date Jul 26, 2007
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Having a Fully Silicided Gate Electrode and Me...
- Publication number 20070063294
- Publication date Mar 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods to facilitate etch uniformity and selectivity
- Publication number 20070042599
- Publication date Feb 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Ting Y. Tsui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration scheme for using silicided dual work function metal gates
- Publication number 20050260841
- Publication date Nov 24, 2005
- Texas Instruments, Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Plasma treatment for silicon-based dielectrics
- Publication number 20050255687
- Publication date Nov 17, 2005
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
In-situ etch-stop etch and ashing in association with damascene pro...
- Publication number 20050245074
- Publication date Nov 3, 2005
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a fully silicided gate electrode and me...
- Publication number 20050215055
- Publication date Sep 29, 2005
- Texas Instruments, Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a semiconductor device having a silicided...
- Publication number 20050215037
- Publication date Sep 29, 2005
- Texas Instruments, Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barc etch comprising a selective etch chemistry and a high polymeri...
- Publication number 20040185655
- Publication date Sep 23, 2004
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual cap layer in damascene interconnection processes
- Publication number 20040127016
- Publication date Jul 1, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Hyesook Hoog
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming single damascene via or trench cavities and for...
- Publication number 20040110369
- Publication date Jun 10, 2004
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO DETERMINE A COMPLETE ETCH IN INTEGRATED DEVICES
- Publication number 20030203516
- Publication date Oct 30, 2003
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming vias and trenches with controlled SiC etch rate...
- Publication number 20030181034
- Publication date Sep 25, 2003
- Ping Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Etching systems and processing gas specie modulation
- Publication number 20030073312
- Publication date Apr 17, 2003
- Francis G. Celii
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Low damage low-k dielectric etch

Method of fabricating semiconductors

Capacitor combination stress testing

Method of fabricating semiconductors

Method and system for controlling the uniformity of a ballistic ele...

Poison-free and low ULK damage integration scheme for damascene int...

FUSI integration method using SOG as a sacrificial planarization layer

Poison-free and low ULK damage integration scheme for damascene int...

Plasma treatment and repair processes for reducing sidewall damage...

FUSI integration method using SOG as a sacrificial planarization layer

FUSI integration method using SOG as a sacrificial planarization layer

Gas switching during an etch process to modulate the characteristic...

Etching systems and processing gas specie modulation

Methods to facilitate etch uniformity and selectivity

Method for manufacturing a semiconductor device having a silicided...

Gas switching during an etch process to modulate the characteristic...

Plasma treatment for silicon-based dielectrics

Methods for forming single damascene via or trench cavities and for...

Integration scheme for using silicided dual work function metal gates

Semiconductor device having a fully silicided gate electrode and me...

Dual cap layer in damascene interconnection processes

BARC etch comprising a selective etch chemistry and a high polymeri...

In-situ plasma ash/treatment after via etch of low-k films for pois...

Method to determine a complete etch in integrated devices

Assembly and method for improved scanning electron microscope analy...

Plasma treatment of low-k dielectric films to improve patterning

Defect and etch rate control in trench etch for dual damascene patt...

Damascene cap layer process for integrated circuit interconnects

Patents Applicationslast 30 patents

LOW DAMAGE LOW-K DIELECTRIC ETCH

METHOD OF FABRICATING SEMICONDUCTORS

CAPACITOR COMBINATION STRESS TESTING

POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INT...

SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION

FUSI Integration Method Using SOG as a Sacrificial Planarization Layer

FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER

SiC Film for Semiconductor Processing

Silicon Carbide Doped Oxide Hardmask For Single and Dual Damascene...

PLASMA TREATMENT AND REPAIR PROCESSES FOR REDUCING SIDEWALL DAMAGE...

POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INT...

DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATI...

Gas switching during an etch process to modulate the characteristic...

METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FAB...

Method and system for controlling the uniformity of a ballistic ele...

GAS SWITCHING DURING AN ETCH PROCESS TO MODULATE THE CHARACTERISTIC...

FUSI integration method using SOG as a sacrificial planarization layer

Semiconductor Device Having a Fully Silicided Gate Electrode and Me...

Methods to facilitate etch uniformity and selectivity

Integration scheme for using silicided dual work function metal gates

Plasma treatment for silicon-based dielectrics

In-situ etch-stop etch and ashing in association with damascene pro...

Semiconductor device having a fully silicided gate electrode and me...

Method for manufacturing a semiconductor device having a silicided...

Barc etch comprising a selective etch chemistry and a high polymeri...

Dual cap layer in damascene interconnection processes

Methods for forming single damascene via or trench cavities and for...

METHOD TO DETERMINE A COMPLETE ETCH IN INTEGRATED DEVICES

Methods for forming vias and trenches with controlled SiC etch rate...

Etching systems and processing gas specie modulation