Ping Ping OOI

Person

Butterworth, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Integrating system in package (SiP) with input/output (IO) board fo...
- Patent number 12,002,793
- Issue date Jun 4, 2024
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate with gradiated dielectric for reducing impedance mismatch
- Patent number 11,837,458
- Issue date Dec 5, 2023
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect core
- Patent number 11,355,458
- Issue date Jun 7, 2022
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate with gradiated dielectric for reducing impedance mismatch
- Patent number 11,164,827
- Issue date Nov 2, 2021
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged die stacks with stacked capacitors and methods of assembli...
- Patent number 11,121,074
- Issue date Sep 14, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating system in package (SiP) with input/output (IO) board fo...
- Patent number 11,114,421
- Issue date Sep 7, 2021
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Over-molded IC package with in-mold capacitor
- Patent number 10,998,261
- Issue date May 4, 2021
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-conductor interconnect structure for a microelectronic device
- Patent number 10,980,108
- Issue date Apr 13, 2021
- Intel Corporation
- Ping Ping Ooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked dice systems
- Patent number 10,916,524
- Issue date Feb 9, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged die stacks with stacked capacitors and methods of assembli...
- Patent number 10,593,618
- Issue date Mar 17, 2020
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Over-molded IC packages with embedded voltage reference plane and h...
- Patent number 10,541,200
- Issue date Jan 21, 2020
- Intel Corporation
- Ping Ping Ooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked package assembly with voltage reference plane
- Patent number 10,403,604
- Issue date Sep 3, 2019
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating system in package (SIP) with input/output (IO) board fo...
- Patent number 10,388,636
- Issue date Aug 20, 2019
- Intel Corporation
- Eng Huat Goh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus utilizing computer on package construction
- Patent number 10,317,938
- Issue date Jun 11, 2019
- Intel Corporation
- Eng Huat Goh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid package transmission line circuits
- Patent number 9,543,244
- Issue date Jan 10, 2017
- Intel Corporation
- Chung Peng Jackson Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid package transmission line circuits
- Patent number 8,890,302
- Issue date Nov 18, 2014
- Intel Corporation
- Chung Peng (Jackson) Kong
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
- Publication number 20220102295
- Publication date Mar 31, 2022
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...
- Publication number 20210366883
- Publication date Nov 25, 2021
- Intel Corporation
- Eng Huat Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLI...
- Publication number 20210005547
- Publication date Jan 7, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DICE SYSTEMS
- Publication number 20200083194
- Publication date Mar 12, 2020
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CONDUCTOR INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE
- Publication number 20200084880
- Publication date Mar 12, 2020
- Intel Corporation
- Ping Ping Ooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONICS PACKAGE WITH A COMBINATION HEAT SPREADER/RADIO FRE...
- Publication number 20200027813
- Publication date Jan 23, 2020
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...
- Publication number 20190378828
- Publication date Dec 12, 2019
- Intel Corporation
- Eng Huat Goh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
- Publication number 20190355681
- Publication date Nov 21, 2019
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE STACKED INTERCONNECTS FOR HIGH-SPEED APPLICATIONS AND MET...
- Publication number 20190311978
- Publication date Oct 10, 2019
- Intel Corporation
- Bok Eng Cheah
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLI...
- Publication number 20190006277
- Publication date Jan 3, 2019
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OVER-MOLDED IC PACKAGES WITH EMBEDDED VOLTAGE REFERENCE PLANE & HEA...
- Publication number 20180366407
- Publication date Dec 20, 2018
- Intel Corporation
- Ping Ping OOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OVER-MOLDED IC PACKAGE WITH IN-MOLD CAPACITOR
- Publication number 20180358292
- Publication date Dec 13, 2018
- Intel Corporation
- Jackson Chung Peng KONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...
- Publication number 20180331081
- Publication date Nov 15, 2018
- Intel Corporation
- Eng Huat Goh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE
- Publication number 20180294252
- Publication date Oct 11, 2018
- Intel Corporation
- Bok Eng CHEAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED VOLTAGE REFERENCE PLANE FOR SYSTEM-IN-PACKAGE APPLICATIONS
- Publication number 20180226357
- Publication date Aug 9, 2018
- Intel Corporation
- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE INCLUDING STRUCTURES TO COUPLE A CAPACITOR TO A PACKAGED...
- Publication number 20170086298
- Publication date Mar 23, 2017
- Tin Poay Chuah
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
APPARATUS UTILIZING COMPUTER ON PACKAGE CONSTRUCTION
- Publication number 20160216731
- Publication date Jul 28, 2016
- Intel Corporation
- Eng Huat Goh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PACKAGE TRANSMISSION LINE CIRCUITS
- Publication number 20150069629
- Publication date Mar 12, 2015
- Chung Peng Jackson KONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PACKAGE TRANSMISSION LINE CIRCUITS
- Publication number 20140001643
- Publication date Jan 2, 2014
- Chung Peng (Jackson) KONG
- H01 - BASIC ELECTRIC ELEMENTS

Ping Ping OOI

Person

Patents Grantslast 30 patents

Integrating system in package (SiP) with input/output (IO) board fo...

Substrate with gradiated dielectric for reducing impedance mismatch

Interconnect core

Substrate with gradiated dielectric for reducing impedance mismatch

Packaged die stacks with stacked capacitors and methods of assembli...

Integrating system in package (SiP) with input/output (IO) board fo...

Over-molded IC package with in-mold capacitor

Multi-conductor interconnect structure for a microelectronic device

Stacked dice systems

Packaged die stacks with stacked capacitors and methods of assembli...

Over-molded IC packages with embedded voltage reference plane and h...

Stacked package assembly with voltage reference plane

Integrating system in package (SIP) with input/output (IO) board fo...

Apparatus utilizing computer on package construction

Hybrid package transmission line circuits

Hybrid package transmission line circuits

Patents Applicationslast 30 patents

SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH

INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...

PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLI...

STACKED DICE SYSTEMS

MULTI-CONDUCTOR INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE

MICROELECTRONICS PACKAGE WITH A COMBINATION HEAT SPREADER/RADIO FRE...

INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...

SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH

COMPOSITE STACKED INTERCONNECTS FOR HIGH-SPEED APPLICATIONS AND MET...

PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLI...

OVER-MOLDED IC PACKAGES WITH EMBEDDED VOLTAGE REFERENCE PLANE & HEA...

OVER-MOLDED IC PACKAGE WITH IN-MOLD CAPACITOR

INTEGRATING SYSTEM IN PACKAGE (SIP) WITH INPUT/OUTPUT (IO) BOARD FO...

STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE

EMBEDDED VOLTAGE REFERENCE PLANE FOR SYSTEM-IN-PACKAGE APPLICATIONS

SUBSTRATE INCLUDING STRUCTURES TO COUPLE A CAPACITOR TO A PACKAGED...

APPARATUS UTILIZING COMPUTER ON PACKAGE CONSTRUCTION

HYBRID PACKAGE TRANSMISSION LINE CIRCUITS

HYBRID PACKAGE TRANSMISSION LINE CIRCUITS