Piyush Sagdeo

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for evaluating integrity of adjacent sub blocks...
- Patent number 11,984,181
- Issue date May 14, 2024
- Western Digital Technologies, Inc.
- Srinivasan Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
UECC failure handling method
- Patent number 11,704,190
- Issue date Jul 18, 2023
- Western Digital Technologies, Inc.
- Ramkumar Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction scheme in flash memory
- Patent number 10,936,415
- Issue date Mar 2, 2021
- Western Digital Technologies, Inc.
- Chris Yip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System handling for first read read disturb
- Patent number 10,790,031
- Issue date Sep 29, 2020
- Western Digital Technologies, Inc.
- Piyush Sagdeo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub block mode read scrub design for non-volatile memory
- Patent number 10,734,079
- Issue date Aug 4, 2020
- Western Digital Technologies, Inc.
- Srinivasan Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor threshold voltage maintenance in 3D memory
- Patent number 10,691,372
- Issue date Jun 23, 2020
- Western Digital Technologies, Inc.
- Srinivasan Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-read voltage pulse for first read error handling
- Patent number 10,235,294
- Issue date Mar 19, 2019
- SanDisk Technologies LLC
- Ching-Huang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial bad block detection and re-use using EPWR for block based a...
- Patent number 9,804,922
- Issue date Oct 31, 2017
- SanDisk Technologies LLC
- Mrinal Kochar
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive EPWR (enhanced post write read) scheduling
- Patent number 9,235,470
- Issue date Jan 12, 2016
- SanDisk Technologies, Inc
- Abhijeet Bhalerao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced dynamic read process with single-level cell segmentation
- Patent number 9,195,587
- Issue date Nov 24, 2015
- SanDisk Technologies Inc.
- Mrinal Kochar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM RECOVERY DURING CGI-WL DEFECT
- Publication number 20240176705
- Publication date May 30, 2024
- Western Digital Technologies, Inc.
- Mahim Raj GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UECC Failure Handling Method
- Publication number 20230130369
- Publication date Apr 27, 2023
- Western Digital Technologies, Inc.
- Ramkumar SUBRAMANIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems And Methods For Evaluating Integrity Of Adjacent Sub Blocks...
- Publication number 20200409808
- Publication date Dec 31, 2020
- Western Digital Technologies, Inc.
- Srinivasan Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION SCHEME IN FLASH MEMORY
- Publication number 20200409787
- Publication date Dec 31, 2020
- Western Digital Technologies, Inc.
- Chris Yip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR THRESHOLD VOLTAGE MAINTENANCE IN 3D MEMORY
- Publication number 20200183610
- Publication date Jun 11, 2020
- Western Digital Technologies, Inc.
- Srinivasan Seetharaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL BAD BLOCK DETECTION AND RE-USE USING EPWR FOR BLOCK BASED A...
- Publication number 20160019111
- Publication date Jan 21, 2016
- SANDISK TECHNOLOGIES INC.
- Mrinal Kochar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING
- Publication number 20150100851
- Publication date Apr 9, 2015
- Abhijeet Bhalerao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Dynamic Read Process with Single-Level Cell Segmentation
- Publication number 20140258590
- Publication date Sep 11, 2014
- Mrinal Kochar
- G06 - COMPUTING CALCULATING COUNTING

Piyush Sagdeo

Person

Patents Grantslast 30 patents

Systems and methods for evaluating integrity of adjacent sub blocks...

UECC failure handling method

Error correction scheme in flash memory

System handling for first read read disturb

Sub block mode read scrub design for non-volatile memory

Transistor threshold voltage maintenance in 3D memory

Pre-read voltage pulse for first read error handling

Partial bad block detection and re-use using EPWR for block based a...

Adaptive EPWR (enhanced post write read) scheduling

Enhanced dynamic read process with single-level cell segmentation

Patents Applicationslast 30 patents

SYSTEM RECOVERY DURING CGI-WL DEFECT

UECC Failure Handling Method

Systems And Methods For Evaluating Integrity Of Adjacent Sub Blocks...

ERROR CORRECTION SCHEME IN FLASH MEMORY

TRANSISTOR THRESHOLD VOLTAGE MAINTENANCE IN 3D MEMORY

PARTIAL BAD BLOCK DETECTION AND RE-USE USING EPWR FOR BLOCK BASED A...

ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING

Enhanced Dynamic Read Process with Single-Level Cell Segmentation