Pradeep Kanapathipillai

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
DSB operation with excluded region
- Patent number 12,321,746
- Issue date Jun 3, 2025
- Apple Inc.
- Jeff Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,174,785
- Issue date Dec 24, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency management in synchronization events
- Patent number 11,914,524
- Issue date Feb 27, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic voltage and frequency scaling (DVFS) within processor clusters
- Patent number 11,797,045
- Issue date Oct 24, 2023
- QUALCOMM Incorporated
- Jonathan Masters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSB operation with excluded region
- Patent number 11,720,360
- Issue date Aug 8, 2023
- Apple Inc.
- Jeff Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified address translation
- Patent number 11,221,962
- Issue date Jan 11, 2022
- Apple Inc.
- Jeffry E. Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architected state retention for a frequent operating state switchin...
- Patent number 10,990,159
- Issue date Apr 27, 2021
- Apple Inc.
- Bernard Joseph Semeria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer invalidation by range
- Patent number 10,725,928
- Issue date Jul 28, 2020
- Apple Inc.
- Brian R. Mestan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified prefetch circuit for multi-level caches
- Patent number 10,621,100
- Issue date Apr 14, 2020
- Apple Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load/store dependency predictor optimization for replayed loads
- Patent number 10,437,595
- Issue date Oct 8, 2019
- Apple Inc.
- Pradeep Kanapathipillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out of order store commit
- Patent number 10,228,951
- Issue date Mar 12, 2019
- Apple Inc.
- Kulin N. Kothari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified prefetch circuit for multi-level caches
- Patent number 10,180,905
- Issue date Jan 15, 2019
- Apple Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-store unit with banked queue
- Patent number 10,133,571
- Issue date Nov 20, 2018
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution unit power management
- Patent number 10,037,073
- Issue date Jul 31, 2018
- Apple Inc.
- Edvin Catovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access permissions modification
- Patent number 9,852,084
- Issue date Dec 26, 2017
- Apple Inc.
- Peter G. Soderquist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency for pointer chasing loads
- Patent number 9,710,268
- Issue date Jul 18, 2017
- Apple Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Completing load and store instructions in a weakly-ordered memory m...
- Patent number 9,535,695
- Issue date Jan 3, 2017
- Apple Inc.
- John H. Mylius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for allowing speculative execution of loads beyond a wait...
- Patent number 9,501,284
- Issue date Nov 22, 2016
- Apple Inc.
- Pradeep Kanapathipillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical clock control using hysterisis and threshold management
- Patent number 9,494,997
- Issue date Nov 15, 2016
- Apple Inc.
- Kulin N. Kothari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load ordering in a weakly-ordered processor
- Patent number 9,383,995
- Issue date Jul 5, 2016
- Apple Inc.
- Pradeep Kanapathipillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delaying cache data array updates
- Patent number 9,229,866
- Issue date Jan 5, 2016
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient handling of misaligned loads and stores
- Patent number 9,131,899
- Issue date Sep 15, 2015
- Apple Inc.
- Hari S. Kannan
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Coordinated prefetching based on training in hierarchically cached...
- Patent number 9,098,418
- Issue date Aug 4, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching across page boundaries in hierarchically cached processors
- Patent number 9,047,198
- Issue date Jun 2, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache policies for uncacheable memory requests
- Patent number 9,043,554
- Issue date May 26, 2015
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor employing split scheduler in which near, low latency oper...
- Patent number 8,364,936
- Issue date Jan 29, 2013
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor employing split scheduler in which near, low latency oper...
- Patent number 8,255,671
- Issue date Aug 28, 2012
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PERFORMING THERMAL MANAGEMENT BASED ON TEMPERATURE EVOLUTION MODELS...
- Publication number 20250224787
- Publication date Jul 10, 2025
- QUALCOMM Incorporated
- Mahadevamurty Nemani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS INCLUDING POWER CONTROL CIRCUITS TO REDUCE A NO-LOAD VOL...
- Publication number 20250093942
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Mahadevamurty Nemani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20250094381
- Publication date Mar 20, 2025
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING TELEMETRY VALUES INTO COMMON DATA FORMATS IN A PROCESSOR...
- Publication number 20240427682
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Sagar Koorapati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSB Operation with Excluded Region
- Publication number 20230333851
- Publication date Oct 19, 2023
- Apple Inc.
- Jeff Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Management in Synchronization Events
- Publication number 20230281133
- Publication date Sep 7, 2023
- NUVIA, INC.
- Adrian MONTERO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Voltage and Frequency Scaling (DVFS) within Processor Clusters
- Publication number 20230093426
- Publication date Mar 23, 2023
- NUVIA, INC.
- Jonathan MASTERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES
- Publication number 20230064603
- Publication date Mar 2, 2023
- NUVIA, INC.
- Conrado BLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220358082
- Publication date Nov 10, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSB Operation with Excluded Region
- Publication number 20220083338
- Publication date Mar 17, 2022
- Apple Inc.
- Jeff Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED ADDRESS TRANSLATION
- Publication number 20210064539
- Publication date Mar 4, 2021
- Apple Inc.
- Jeffry E. Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20200272597
- Publication date Aug 27, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Translation Lookaside Buffer Invalidation By Range
- Publication number 20200218663
- Publication date Jul 9, 2020
- Apple Inc.
- Brian R. Mestan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTED STATE RETENTION
- Publication number 20180307297
- Publication date Oct 25, 2018
- Apple Inc.
- Bernard Joseph Semeria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK CONTROL USING HYSTERISIS AND THRESHOLD MANAGEMENT
- Publication number 20150362978
- Publication date Dec 17, 2015
- Apple Inc.
- Kulin N. Kothari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY FOR POINTER CHASING LOADS
- Publication number 20150309792
- Publication date Oct 29, 2015
- Apple Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAYING CACHE DATA ARRAY UPDATES
- Publication number 20150149722
- Publication date May 28, 2015
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLETING LOAD AND STORE INSTRUCTIONS IN A WEAKLY-ORDERED MEMORY M...
- Publication number 20140215190
- Publication date Jul 31, 2014
- Apple Inc.
- John H. Mylius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD ORDERING IN A WEAKLY-ORDERED PROCESSOR
- Publication number 20140215191
- Publication date Jul 31, 2014
- Apple Inc.
- Pradeep Kanapathipillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS
- Publication number 20140181403
- Publication date Jun 26, 2014
- Apple Inc.
- Brian P. Lilly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING ACROSS PAGE BOUNDARIES IN HIERARCHICALLY CACHED PROCESSORS
- Publication number 20140149632
- Publication date May 29, 2014
- Apple Inc.
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATED PREFETCHING IN HIERARCHICALLY CACHED PROCESSORS
- Publication number 20130254485
- Publication date Sep 26, 2013
- Hari S. Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT HANDLING OF MISALIGNED LOADS AND STORES
- Publication number 20130013862
- Publication date Jan 10, 2013
- Hari S. Kannan
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Split Scheduler
- Publication number 20120290818
- Publication date Nov 15, 2012
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split Scheduler
- Publication number 20100162262
- Publication date Jun 24, 2010
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING

Pradeep Kanapathipillai

Person

Patents Grantslast 30 patents

DSB operation with excluded region

Coprocessors with bypass optimization, variable grid architecture,...

Latency management in synchronization events

Dynamic voltage and frequency scaling (DVFS) within processor clusters

DSB operation with excluded region

Unified address translation

Architected state retention for a frequent operating state switchin...

Translation lookaside buffer invalidation by range

Unified prefetch circuit for multi-level caches

Load/store dependency predictor optimization for replayed loads

Out of order store commit

Unified prefetch circuit for multi-level caches

Load-store unit with banked queue

Execution unit power management

Access permissions modification

Reducing latency for pointer chasing loads

Completing load and store instructions in a weakly-ordered memory m...

Mechanism for allowing speculative execution of loads beyond a wait...

Hierarchical clock control using hysterisis and threshold management

Load ordering in a weakly-ordered processor

Delaying cache data array updates

Efficient handling of misaligned loads and stores

Coordinated prefetching based on training in hierarchically cached...

Prefetching across page boundaries in hierarchically cached processors

Cache policies for uncacheable memory requests

Processor employing split scheduler in which near, low latency oper...

Processor employing split scheduler in which near, low latency oper...

Patents Applicationslast 30 patents

PERFORMING THERMAL MANAGEMENT BASED ON TEMPERATURE EVOLUTION MODELS...

PROCESSORS INCLUDING POWER CONTROL CIRCUITS TO REDUCE A NO-LOAD VOL...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

CONVERTING TELEMETRY VALUES INTO COMMON DATA FORMATS IN A PROCESSOR...

DSB Operation with Excluded Region

Latency Management in Synchronization Events

Dynamic Voltage and Frequency Scaling (DVFS) within Processor Clusters

SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

DSB Operation with Excluded Region

UNIFIED ADDRESS TRANSLATION

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Translation Lookaside Buffer Invalidation By Range

ARCHITECTED STATE RETENTION

HIERARCHICAL CLOCK CONTROL USING HYSTERISIS AND THRESHOLD MANAGEMENT

REDUCING LATENCY FOR POINTER CHASING LOADS

DELAYING CACHE DATA ARRAY UPDATES

COMPLETING LOAD AND STORE INSTRUCTIONS IN A WEAKLY-ORDERED MEMORY M...

LOAD ORDERING IN A WEAKLY-ORDERED PROCESSOR

CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS

PREFETCHING ACROSS PAGE BOUNDARIES IN HIERARCHICALLY CACHED PROCESSORS

COORDINATED PREFETCHING IN HIERARCHICALLY CACHED PROCESSORS

EFFICIENT HANDLING OF MISALIGNED LOADS AND STORES

Split Scheduler

Split Scheduler