Pradeep Nagarajan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
SERDES built-in sinusoidal jitter injection
- Patent number 10,084,591
- Issue date Sep 25, 2018
- Oracle International Corporation
- Chaitanya Palusa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-die input reference voltage with self-calibrating duty cycle cor...
- Patent number 9,711,189
- Issue date Jul 18, 2017
- Altera Corporation
- Bonnie I. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 9,158,873
- Issue date Oct 13, 2015
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 9,059,716
- Issue date Jun 16, 2015
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits and methods for providing clock signals
- Patent number 8,847,626
- Issue date Sep 30, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 8,787,097
- Issue date Jul 22, 2014
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 8,680,905
- Issue date Mar 25, 2014
- Altera Corporation
- Pradeep Nagarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty cycle correction circuit for memory interfaces in integrated c...
- Patent number 8,624,647
- Issue date Jan 7, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variation compensation circuitry for memory interface
- Patent number 8,565,034
- Issue date Oct 22, 2013
- Altera Corporation
- Sean Shau-Tu Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for generating PVT compensated phase offset to improve a...
- Patent number 8,237,475
- Issue date Aug 7, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing multiple delay paths in a delay circuit
- Patent number 8,159,277
- Issue date Apr 17, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing reduced duty cycle distortion
- Patent number 8,130,016
- Issue date Mar 6, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing multiple delay paths in a delay circuit
- Patent number 7,893,739
- Issue date Feb 22, 2011
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SERDES BUILT-IN SINUSOIDAL JITTER INJECTION
- Publication number 20180278406
- Publication date Sep 27, 2018
- Oracle International Corporation
- Chaitanya Palusa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...
- Publication number 20110175657
- Publication date Jul 21, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques for Providing Reduced Duty Cycle Distortion
- Publication number 20110074477
- Publication date Mar 31, 2011
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY

Pradeep Nagarajan

Person

Patents Grantslast 30 patents

SERDES built-in sinusoidal jitter injection

On-die input reference voltage with self-calibrating duty cycle cor...

Circuit design technique for DQS enable/disable calibration

Digital PVT compensation for delay chain

Circuits and methods for providing clock signals

Circuit design technique for DQS enable/disable calibration

Digital PVT compensation for delay chain

Duty cycle correction circuit for memory interfaces in integrated c...

Variation compensation circuitry for memory interface

Techniques for generating PVT compensated phase offset to improve a...

Techniques for providing multiple delay paths in a delay circuit

Techniques for providing reduced duty cycle distortion

Techniques for providing multiple delay paths in a delay circuit

Patents Applicationslast 30 patents

SERDES BUILT-IN SINUSOIDAL JITTER INJECTION

DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...

Techniques for Providing Reduced Duty Cycle Distortion