Pradeep R. Trivedi

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 11,023,403
- Issue date Jun 1, 2021
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip to chip interface with scalable bandwidth
- Patent number 10,521,391
- Issue date Dec 31, 2019
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital on-chip duty cycle monitoring device
- Patent number 10,241,537
- Issue date Mar 26, 2019
- Apple Inc.
- Huaimin Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular programmable delay line blocks for use in a delay locked loop
- Patent number 8,373,470
- Issue date Feb 12, 2013
- Apple Inc.
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop including a mechanism for reducing lock time
- Patent number 8,368,444
- Issue date Feb 5, 2013
- Apple Inc.
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 8,341,578
- Issue date Dec 25, 2012
- Apple Inc.
- Brian J. Campbell
- G01 - MEASURING TESTING
Information Patent Grant
Low latency flop circuit
- Patent number 8,026,754
- Issue date Sep 27, 2011
- Apple Inc.
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gater with test features and low setup time
- Patent number 7,779,372
- Issue date Aug 17, 2010
- Apple Inc.
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for receiver circuit tuning
- Patent number 7,263,628
- Issue date Aug 28, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to store delay locked loop biasing parameters
- Patent number 7,251,305
- Issue date Jul 31, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensation technique to mitigate aging effects in integrated circ...
- Patent number 7,129,800
- Issue date Oct 31, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustment and calibration system for post-fabrication treatment of...
- Patent number 7,106,113
- Issue date Sep 12, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded integrated circuit aging sensor system
- Patent number 7,054,787
- Issue date May 30, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Calibration technique for phase locked loop leakage current
- Patent number 6,998,887
- Issue date Feb 14, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Region-based voltage drop budgets for low-power design
- Patent number 6,976,235
- Issue date Dec 13, 2005
- Sun Microsystems, Inc.
- Sudhakar Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level reduction of clock skew based on local thermal profiling
- Patent number 6,973,398
- Issue date Dec 6, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Accuracy of timing analysis using region-based voltage drop budgets
- Patent number 6,971,079
- Issue date Nov 29, 2005
- Sun Microsystems, Inc.
- Gin Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for in-situ signal delay measurement for a microp...
- Patent number 6,954,913
- Issue date Oct 11, 2005
- Sun Microsystems Inc
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Duty cycle corrector
- Patent number 6,882,196
- Issue date Apr 19, 2005
- Sun Microsystems, Inc.
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop design with diode for loop filter capacitance lea...
- Patent number 6,861,885
- Issue date Mar 1, 2005
- Sun Microsystems, Inc.
- Pradeep Trivedi
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Self-correcting I/O interface driver scheme for memory interface
- Patent number 6,859,068
- Issue date Feb 22, 2005
- Sun Microsystems, Inc.
- Pradeep Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
DLL static phase error measurement technique
- Patent number 6,829,548
- Issue date Dec 7, 2004
- Sun Microsystems, Inc.
- Priya Ananthanarayanan
- G01 - MEASURING TESTING
Information Patent Grant
Jitter estimation for a phase locked loop
- Patent number 6,819,192
- Issue date Nov 16, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variation reduction technique for charge pump transistor aging
- Patent number 6,812,755
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Negative bias temperature instability correction technique for dela...
- Patent number 6,812,758
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Increasing power supply noise rejection using linear voltage regula...
- Patent number 6,809,557
- Issue date Oct 26, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G05 - CONTROLLING REGULATING
Information Patent Grant
Quantifying a difference between nodal voltages
- Patent number 6,806,698
- Issue date Oct 19, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for calibrating a delay locked loop charge pum...
- Patent number 6,788,045
- Issue date Sep 7, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transmission gate based signal transition accelerator
- Patent number 6,784,689
- Issue date Aug 31, 2004
- Sun Microsystems, Inc.
- Sudhakar Bobba
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Post-silicon phase offset control of phase locked loop input receiver
- Patent number 6,784,752
- Issue date Aug 31, 2004
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH
- Publication number 20200183874
- Publication date Jun 11, 2020
- Apple Inc.
- Jafar Savoj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL ON-CHIP DUTY CYCLE MONITORING DEVICE
- Publication number 20180364752
- Publication date Dec 20, 2018
- Apple Inc.
- Huaimin Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Locked Loop Including a Mechanism for Reducing Lock Time
- Publication number 20120086484
- Publication date Apr 12, 2012
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Modular Programmable Delay Line Blocks for Use in a Delay Locked Loop
- Publication number 20120086485
- Publication date Apr 12, 2012
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20100277219
- Publication date Nov 4, 2010
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY FLOP CIRCUIT
- Publication number 20100207677
- Publication date Aug 19, 2010
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Gater with Test Features and Low Setup Time
- Publication number 20080180159
- Publication date Jul 31, 2008
- Brian J. Campbell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compensation technique to mitigate aging effects in integrated circ...
- Publication number 20050168255
- Publication date Aug 4, 2005
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-CORRECTING I/O INTERFACE DRIVER SCHEME FOR MEMORY INTERFACE
- Publication number 20050030064
- Publication date Feb 10, 2005
- Pradeep Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DLL Static phase error measurement technique
- Publication number 20040199345
- Publication date Oct 7, 2004
- Priya Ananthanarayanan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for in-situ signal delay measurement for a microp...
- Publication number 20040196069
- Publication date Oct 7, 2004
- SUN MICROSYSTEMS, INC.
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Single edge-triggered flip-flop design with asynchronous programmab...
- Publication number 20040187086
- Publication date Sep 23, 2004
- Pradeep R. Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System level reduction of clock skew based on local thermal profiling
- Publication number 20040181354
- Publication date Sep 16, 2004
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for receiver circuit tuning
- Publication number 20040177286
- Publication date Sep 9, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGATIVE BIAS TEMPERATURE INSTABILITY CORRECTION TECHNIQUE FOR DELA...
- Publication number 20040155696
- Publication date Aug 12, 2004
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Embedded integrated circuit aging sensor System
- Publication number 20040148111
- Publication date Jul 29, 2004
- Claude R. Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Variation reduction technique for charge pump transistor aging
- Publication number 20040145396
- Publication date Jul 29, 2004
- Gin S. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Region-based voltage drop budgets for low-power design
- Publication number 20040054979
- Publication date Mar 18, 2004
- Sudhakar Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accuracy of timing analysis using region-based voltage drop budgets
- Publication number 20040054975
- Publication date Mar 18, 2004
- Gin Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibration technique for phase locked loop leakage current
- Publication number 20040033793
- Publication date Feb 19, 2004
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Duty cycle corrector
- Publication number 20040012428
- Publication date Jan 22, 2004
- Gin Yee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...
- Publication number 20040012421
- Publication date Jan 22, 2004
- Pradeep Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...
- Publication number 20040012426
- Publication date Jan 22, 2004
- Pradeep Trivedi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic modulation of on-chip supply voltage for low-power design
- Publication number 20030223301
- Publication date Dec 4, 2003
- Pradeep Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Clock skew reduction using active shields
- Publication number 20030221174
- Publication date Nov 27, 2003
- Pradeep R. Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for calibration of a post-fabrication bias vol...
- Publication number 20030214362
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustment and calibration system for post-fabrication treatment of...
- Publication number 20030214333
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustment and calibration system for post-fabrication treatment of...
- Publication number 20030215042
- Publication date Nov 20, 2003
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjustment and calibration system for post-fabrication treatment of...
- Publication number 20030214998
- Publication date Nov 20, 2003
- Claude Gauthier
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for calibrating a delay locked loop charge pum...
- Publication number 20030214280
- Publication date Nov 20, 2003
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY

Pradeep R. Trivedi

Person

Patents Grantslast 30 patents

Chip to chip interface with scalable bandwidth

Chip to chip interface with scalable bandwidth

Digital on-chip duty cycle monitoring device

Modular programmable delay line blocks for use in a delay locked loop

Delay locked loop including a mechanism for reducing lock time

Clock gater with test features and low setup time

Low latency flop circuit

Clock gater with test features and low setup time

Method and apparatus for receiver circuit tuning

Method and apparatus to store delay locked loop biasing parameters

Compensation technique to mitigate aging effects in integrated circ...

Adjustment and calibration system for post-fabrication treatment of...

Embedded integrated circuit aging sensor system

Calibration technique for phase locked loop leakage current

Region-based voltage drop budgets for low-power design

System level reduction of clock skew based on local thermal profiling

Accuracy of timing analysis using region-based voltage drop budgets

System and method for in-situ signal delay measurement for a microp...

Duty cycle corrector

Phase locked loop design with diode for loop filter capacitance lea...

Self-correcting I/O interface driver scheme for memory interface

DLL static phase error measurement technique

Jitter estimation for a phase locked loop

Variation reduction technique for charge pump transistor aging

Negative bias temperature instability correction technique for dela...

Increasing power supply noise rejection using linear voltage regula...

Quantifying a difference between nodal voltages

Method and apparatus for calibrating a delay locked loop charge pum...

Transmission gate based signal transition accelerator

Post-silicon phase offset control of phase locked loop input receiver

Patents Applicationslast 30 patents

CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH

DIGITAL ON-CHIP DUTY CYCLE MONITORING DEVICE

Delay Locked Loop Including a Mechanism for Reducing Lock Time

Modular Programmable Delay Line Blocks for Use in a Delay Locked Loop

Clock Gater with Test Features and Low Setup Time

LOW LATENCY FLOP CIRCUIT

Clock Gater with Test Features and Low Setup Time

Compensation technique to mitigate aging effects in integrated circ...

SELF-CORRECTING I/O INTERFACE DRIVER SCHEME FOR MEMORY INTERFACE

DLL Static phase error measurement technique

System and method for in-situ signal delay measurement for a microp...

Single edge-triggered flip-flop design with asynchronous programmab...

System level reduction of clock skew based on local thermal profiling

Method and apparatus for receiver circuit tuning

NEGATIVE BIAS TEMPERATURE INSTABILITY CORRECTION TECHNIQUE FOR DELA...

Embedded integrated circuit aging sensor System

Variation reduction technique for charge pump transistor aging

Region-based voltage drop budgets for low-power design

Accuracy of timing analysis using region-based voltage drop budgets

Calibration technique for phase locked loop leakage current

Duty cycle corrector

PHASE LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...

DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEA...

Dynamic modulation of on-chip supply voltage for low-power design

Clock skew reduction using active shields

Method and apparatus for calibration of a post-fabrication bias vol...

Adjustment and calibration system for post-fabrication treatment of...

Adjustment and calibration system for post-fabrication treatment of...

Adjustment and calibration system for post-fabrication treatment of...

Method and apparatus for calibrating a delay locked loop charge pum...