Prakash Krishnamoorthy

Person

Bethlehem, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction address encoding and decoding based on program construc...
- Patent number 9,348,593
- Issue date May 24, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
At-speed scan testing of interface functional logic of an embedded...
- Patent number 8,924,801
- Issue date Dec 30, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having clock gating circuitry responsive to scan...
- Patent number 8,904,255
- Issue date Dec 2, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Clock control for reducing timing exceptions in scan testing of an...
- Patent number 8,799,731
- Issue date Aug 5, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising scan test circuitry with parallel reo...
- Patent number 8,793,546
- Issue date Jul 29, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry configured for bypassing selected segments of a...
- Patent number 8,726,108
- Issue date May 13, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Coding circuitry for difference-based data transformation
- Patent number 8,711,013
- Issue date Apr 29, 2014
- LSI Corporation
- Prakash Krishnamoorthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan test circuitry configured to prevent capture of potentially no...
- Patent number 8,700,962
- Issue date Apr 15, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with transition control circuitry for limiting s...
- Patent number 8,677,200
- Issue date Mar 18, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Scan test circuitry with delay defect bypass functionality
- Patent number 8,645,778
- Issue date Feb 4, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Low-power and area-efficient scan cell for integrated circuit testing
- Patent number 8,566,658
- Issue date Oct 22, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Local Repair Signature Handling for Repairable Memories
- Publication number 20140281703
- Publication date Sep 18, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED SCAN TESTING OF INTERFACE FUNCTIONAL LOGIC OF AN EMBEDDED...
- Publication number 20140229778
- Publication date Aug 14, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIAT...
- Publication number 20140201584
- Publication date Jul 17, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN...
- Publication number 20140101505
- Publication date Apr 10, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUC...
- Publication number 20140068229
- Publication date Mar 6, 2014
- LSI Corporation
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NO...
- Publication number 20140032985
- Publication date Jan 30, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN...
- Publication number 20130219238
- Publication date Aug 22, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION
- Publication number 20130181852
- Publication date Jul 18, 2013
- LSI Corporation
- Prakash Krishnamoorthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A...
- Publication number 20130185607
- Publication date Jul 18, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Scan Test Circuitry with Delay Defect Bypass Functionality
- Publication number 20130173976
- Publication date Jul 4, 2013
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTI...
- Publication number 20130124594
- Publication date May 16, 2013
- LSI Corporation
- Prakash Krishnamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING S...
- Publication number 20130067290
- Publication date Mar 14, 2013
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REO...
- Publication number 20120324303
- Publication date Dec 20, 2012
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
LOW-POWER AND AREA-EFFICIENT SCAN CELL FOR INTEGRATED CIRCUIT TESTING
- Publication number 20120246529
- Publication date Sep 27, 2012
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING

Prakash Krishnamoorthy

Person

Patents Grantslast 30 patents

Instruction address encoding and decoding based on program construc...

At-speed scan testing of interface functional logic of an embedded...

Integrated circuit having clock gating circuitry responsive to scan...

Clock control for reducing timing exceptions in scan testing of an...

Integrated circuit comprising scan test circuitry with parallel reo...

Scan test circuitry configured for bypassing selected segments of a...

Coding circuitry for difference-based data transformation

Scan test circuitry configured to prevent capture of potentially no...

Integrated circuit with transition control circuitry for limiting s...

Scan test circuitry with delay defect bypass functionality

Low-power and area-efficient scan cell for integrated circuit testing

Patents Applicationslast 30 patents

Local Repair Signature Handling for Repairable Memories

AT-SPEED SCAN TESTING OF INTERFACE FUNCTIONAL LOGIC OF AN EMBEDDED...

SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIAT...

CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN...

INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUC...

SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NO...

INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN...

CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION

SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A...

Scan Test Circuitry with Delay Defect Bypass Functionality

DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTI...

INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING S...

INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REO...

LOW-POWER AND AREA-EFFICIENT SCAN CELL FOR INTEGRATED CIRCUIT TESTING