Prakash Narayanan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,933,844
- Issue date Mar 19, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,921,159
- Issue date Mar 5, 2024
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic generation of ATPG mode signals for testing multipath memor...
- Patent number 11,879,940
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 11,852,683
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Full pad coverage boundary scan
- Patent number 11,821,945
- Issue date Nov 21, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,768,726
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition fault testing of functionally asynchronous paths in an i...
- Patent number 11,709,203
- Issue date Jul 25, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,592,483
- Issue date Feb 28, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 11,555,853
- Issue date Jan 17, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,519,964
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Testing read-only memory using memory built-in self-test controller
- Patent number 11,521,698
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistion fault testing of funtionally asynchronous paths in an i...
- Patent number 11,300,615
- Issue date Apr 12, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Multiple input signature register analysis for digital circuitry
- Patent number 11,209,481
- Issue date Dec 28, 2021
- Texas Instruments Incorporated
- Naman Maheshwari
- G01 - MEASURING TESTING
Information Patent Grant
False path timing exception handler circuit
- Patent number 11,194,944
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,194,645
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional circuitry, decompressor circuitry, scan circuitry, maski...
- Patent number 11,119,152
- Issue date Sep 14, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,073,557
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic generation of ATPG mode signals for testing multipath memor...
- Patent number 11,073,553
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,047,910
- Issue date Jun 29, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full pad coverage boundary scan
- Patent number 10,983,161
- Issue date Apr 20, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 10,866,280
- Issue date Dec 15, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Testing read-only memory using memory built-in self-test controller
- Patent number 10,818,374
- Issue date Oct 27, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
False path timing exception handler circuit
- Patent number 10,776,546
- Issue date Sep 15, 2020
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed scan chains with three input mask gates and registers
- Patent number 10,591,540
- Issue date Mar 17, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 10,579,454
- Issue date Mar 3, 2020
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area efficient parallel test data path for embedded memories
- Patent number 10,460,821
- Issue date Oct 29, 2019
- Texas Instruments Incorporated
- Prakash Narayanan
- G11 - INFORMATION STORAGE
Information Patent Grant
False path timing exception handler circuit
- Patent number 10,331,826
- Issue date Jun 25, 2019
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full pad coverage boundary scan
- Patent number 10,274,538
- Issue date Apr 30, 2019
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Multiple input signature register analysis for digital circuitry
- Patent number 10,184,980
- Issue date Jan 22, 2019
- Texas Instruments Incorporated
- Naman Maheshwari
- G01 - MEASURING TESTING
Information Patent Grant
Compressed scan chains with three input mask gates and registers
- Patent number 9,952,283
- Issue date Apr 24, 2018
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20230194605
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20230152373
- Publication date May 18, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS FOR USING SCAN OPERATIONS TO PROTECT SECURE A...
- Publication number 20220358230
- Publication date Nov 10, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...
- Publication number 20220196738
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20220091919
- Publication date Mar 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20210364569
- Publication date Nov 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...
- Publication number 20210318378
- Publication date Oct 14, 2021
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20210311121
- Publication date Oct 7, 2021
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT
- Publication number 20210278459
- Publication date Sep 9, 2021
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Full Pad Coverage Boundary Scan
- Publication number 20210215757
- Publication date Jul 15, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20210055345
- Publication date Feb 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER
- Publication number 20200388346
- Publication date Dec 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20200372197
- Publication date Nov 26, 2020
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20200355744
- Publication date Nov 12, 2020
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20200309851
- Publication date Oct 1, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20200174069
- Publication date Jun 4, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20200142768
- Publication date May 7, 2020
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER
- Publication number 20200135290
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20190266303
- Publication date Aug 29, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Full Pad Coverage Boundary Scan
- Publication number 20190235020
- Publication date Aug 1, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT
- Publication number 20190204382
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G01 - MEASURING TESTING
Information Patent Application
TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...
- Publication number 20190204387
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...
- Publication number 20190206507
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY
- Publication number 20190113566
- Publication date Apr 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- NAMAN MAHESHWARI
- G01 - MEASURING TESTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20180307553
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20180307788
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20180210030
- Publication date Jul 26, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
- Publication number 20180174663
- Publication date Jun 21, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY
- Publication number 20180067164
- Publication date Mar 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- NAMAN MAHESHWARI
- G01 - MEASURING TESTING
Information Patent Application
Full Pad Coverage Boundary Scan
- Publication number 20180045778
- Publication date Feb 15, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING

Prakash Narayanan

Person

Patents Grantslast 30 patents

Path based controls for ATE mode testing of multicell memory circuit

Compressed scan chain diagnosis by internal chain observation, proc...

Dynamic generation of ATPG mode signals for testing multipath memor...

Scan chain self-testing of lockstep cores on reset

Full pad coverage boundary scan

Delay fault testing of pseudo static controls

Transition fault testing of functionally asynchronous paths in an i...

Compressed scan chain diagnosis by internal chain observation, proc...

Scan chain self-testing of lockstep cores on reset

Phase controlled codec block scan of a partitioned circuit device

Testing read-only memory using memory built-in self-test controller

Transistion fault testing of funtionally asynchronous paths in an i...

Multiple input signature register analysis for digital circuitry

False path timing exception handler circuit

Delay fault testing of pseudo static controls

Functional circuitry, decompressor circuitry, scan circuitry, maski...

Phase controlled codec block scan of a partitioned circuit device

Dynamic generation of ATPG mode signals for testing multipath memor...

Path based controls for ATE mode testing of multicell memory circuit

Full pad coverage boundary scan

Scan chain self-testing of lockstep cores on reset

Testing read-only memory using memory built-in self-test controller

False path timing exception handler circuit

Compressed scan chains with three input mask gates and registers

Delay fault testing of pseudo static controls

Area efficient parallel test data path for embedded memories

False path timing exception handler circuit

Full pad coverage boundary scan

Multiple input signature register analysis for digital circuitry

Compressed scan chains with three input mask gates and registers

Patents Applicationslast 30 patents

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

METHODS AND APPARATUS FOR USING SCAN OPERATIONS TO PROTECT SECURE A...

TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT

Full Pad Coverage Boundary Scan

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

Full Pad Coverage Boundary Scan

PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT

TRANSISTION FAULT TESTING OF FUNTIONALLY ASYNCHRONOUS PATHS IN AN I...

DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...

MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES

MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY

Full Pad Coverage Boundary Scan