Pranav Kalavade

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Variable error correction codeword packing to support bit error rat...
- Patent number 12,106,815
- Issue date Oct 1, 2024
- Intel Coproration
- Ravi Motwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flash memory chip that modulates its program step voltage as a func...
- Patent number 11,923,010
- Issue date Mar 5, 2024
- INTEL NDTM US LLC
- Arash Hazeghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration of a memory device for programming memory cells
- Patent number 11,721,396
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 11,698,725
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, systems, and methods for heating a memory device
- Patent number 11,625,191
- Issue date Apr 11, 2023
- Intel Corporation
- Arash Hazeghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defective bit line management in connection with a memory access
- Patent number 11,429,469
- Issue date Aug 30, 2022
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
String current reduction during multistrobe sensing to reduce read...
- Patent number 11,315,644
- Issue date Apr 26, 2022
- Intel Corporation
- Pranav Kalavade
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for reducing program disturb degradation in flash...
- Patent number 11,270,778
- Issue date Mar 8, 2022
- Intel Corporation
- Han Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 11,182,074
- Issue date Nov 23, 2021
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boosted bitlines for storage cell programmed state verification in...
- Patent number 11,056,203
- Issue date Jul 6, 2021
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense flags in a memory device
- Patent number 11,029,861
- Issue date Jun 8, 2021
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Defective bit line management in connection with a memory access
- Patent number 10,942,799
- Issue date Mar 9, 2021
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Achieving consistent read times in multi-level non-volatile memory
- Patent number 10,871,903
- Issue date Dec 22, 2020
- Intel Corporation
- Anand S. Ramalingam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-sided soft reads
- Patent number 10,839,916
- Issue date Nov 17, 2020
- Intel Corporation
- Zion S. Kwok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program verification time reduction in non-volatile memory devices
- Patent number 10,832,766
- Issue date Nov 10, 2020
- Intel Corporation
- Ali Khakifirooz
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration of a memory device for programming memory cells
- Patent number 10,777,277
- Issue date Sep 15, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase and soft program for vertical NAND flash
- Patent number 10,699,790
- Issue date Jun 30, 2020
- Intel Corporation
- Krishna K. Parat
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 10,658,053
- Issue date May 19, 2020
- Intel Corporation
- Shantanu R Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for reducing program disturb degradation in flash...
- Patent number 10,629,271
- Issue date Apr 21, 2020
- Intel Corporation
- Han Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Transfer of encoded data stored in non-volatile memory for decoding...
- Patent number 10,599,515
- Issue date Mar 24, 2020
- Intel Corporation
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operation of a memory device during programming
- Patent number 10,482,974
- Issue date Nov 19, 2019
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented erase in memory
- Patent number 10,453,535
- Issue date Oct 22, 2019
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for mapping binary to ternary and its reverse
- Patent number 10,454,495
- Issue date Oct 22, 2019
- Intel Corporation
- Ravi H. Motwani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for performing a concurrent multiple page read of...
- Patent number 10,438,656
- Issue date Oct 8, 2019
- Intel Corporation
- Aliasgar S. Madraswala
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer operations in memory
- Patent number 10,430,114
- Issue date Oct 1, 2019
- Micron Technology, Inc.
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sense flags in a memory device
- Patent number 10,409,506
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 10,379,738
- Issue date Aug 13, 2019
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data recovery in memory devices
- Patent number 10,303,571
- Issue date May 28, 2019
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Erase and soft program for vertical NAND flash
- Patent number 10,290,356
- Issue date May 14, 2019
- Intel Corporation
- Krishna K. Parat
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for improving sequential reading in NAND flash
- Patent number 10,289,313
- Issue date May 14, 2019
- Intel Corporation
- Han Liu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FLASH MEMORY CHIP THAT MODULATES ITS PROGRAM STEP VOLTAGE AS A FUNC...
- Publication number 20240135995
- Publication date Apr 25, 2024
- Intel NDTM US LLC
- Arash HAZEGHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20240013840
- Publication date Jan 11, 2024
- Lodestar Licensing Group, LLC
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SYNCHRONOUS INDEPENDENT PLANE READ OPERATION
- Publication number 20230317144
- Publication date Oct 5, 2023
- Intel NDTM US LLC
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE...
- Publication number 20230266910
- Publication date Aug 24, 2023
- Intel NDTM US LLC
- Chang Wan HA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPROVING WRITE UNIFORMITY IN A MEMORY DEVICE
- Publication number 20230154539
- Publication date May 18, 2023
- Intel Corporation
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROV...
- Publication number 20230044991
- Publication date Feb 9, 2023
- Intel Corporation
- Shantanu Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR...
- Publication number 20220310178
- Publication date Sep 29, 2022
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SIMULTANEOUS PROGRAMMING OF MULTIPLE SUB-BLOCKS IN NAND MEMORY STRU...
- Publication number 20220310160
- Publication date Sep 29, 2022
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...
- Publication number 20220155958
- Publication date May 19, 2022
- Micron Technology, Inc.
- SHANTANU R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRING CURRENT REDUCTION DURING MULTISTROBE SENSING TO REDUCE READ...
- Publication number 20220101932
- Publication date Mar 31, 2022
- Intel Corporation
- Pranav Kalavade
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY HAVING IMPROVED PERFORMANCE AS A CONSEQUENCE OF PROGRA...
- Publication number 20220084606
- Publication date Mar 17, 2022
- Intel Corporation
- Xiang YANG
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY CHIP THAT MODULATES ITS PROGRAM STEP VOLTAGE AS A FUNC...
- Publication number 20210304820
- Publication date Sep 30, 2021
- Intel Corporation
- Arash HAZEGHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR HEATING A MEMORY DEVICE
- Publication number 20210240388
- Publication date Aug 5, 2021
- Intel Corporation
- Arash Hazeghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS
- Publication number 20210193200
- Publication date Jun 24, 2021
- Intel Corporation
- Ali KHAKIFIROOZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE ERROR CORRECTION CODEWORD PACKING TO SUPPORT BIT ERROR RAT...
- Publication number 20210082535
- Publication date Mar 18, 2021
- Intel Corporation
- Ravi Motwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS
- Publication number 20210074338
- Publication date Mar 11, 2021
- Intel Corporation
- Ali KHAKIFIROOZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20200402586
- Publication date Dec 24, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH...
- Publication number 20200350028
- Publication date Nov 5, 2020
- Intel Corporation
- HAN ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF...
- Publication number 20200090743
- Publication date Mar 19, 2020
- Intel Corporation
- Aliasgar S. MADRASWALA
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20200066350
- Publication date Feb 27, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE FLAGS IN A MEMORY DEVICE
- Publication number 20190369887
- Publication date Dec 5, 2019
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACHIEVING CONSISTENT READ TIMES IN MULTI-LEVEL NON-VOLATILE MEMORY
- Publication number 20190332277
- Publication date Oct 31, 2019
- Intel Corporation
- Anand S. Ramalingam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH
- Publication number 20190287627
- Publication date Sep 19, 2019
- Intel Corporation
- Krishna K. Parat
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...
- Publication number 20190258404
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- SHANTANU R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE SYSTEM WITH RECONFIGURABLE NUMBER OF BITS PER CELL
- Publication number 20190227751
- Publication date Jul 25, 2019
- Intel Corporation
- Ali KHAKIFIROOZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESUMING STORAGE DIE PROGRAMMING AFTER POWER LOSS
- Publication number 20190103159
- Publication date Apr 4, 2019
- Intel Corporation
- Ali KHAKIFIROOZ
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM VERIFICATION TIME REDUCTION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20190043563
- Publication date Feb 7, 2019
- Ali Khakifirooz
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF...
- Publication number 20190043564
- Publication date Feb 7, 2019
- Intel Corporation
- ALIASGAR S. MADRASWALA
- G11 - INFORMATION STORAGE
Information Patent Application
ONE-SIDED SOFT READS
- Publication number 20190043589
- Publication date Feb 7, 2019
- Intel Corporation
- Zion S. KWOK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH...
- Publication number 20190043594
- Publication date Feb 7, 2019
- Intel Corporation
- HAN ZHAO
- G11 - INFORMATION STORAGE

Pranav Kalavade

Person

Patents Grantslast 30 patents

Variable error correction codeword packing to support bit error rat...

Flash memory chip that modulates its program step voltage as a func...

Configuration of a memory device for programming memory cells

Apparatuses and methods for concurrently accessing multiple memory...

Apparatuses, systems, and methods for heating a memory device

Defective bit line management in connection with a memory access

String current reduction during multistrobe sensing to reduce read...

Method and system for reducing program disturb degradation in flash...

Apparatuses and methods for concurrently accessing multiple memory...

Boosted bitlines for storage cell programmed state verification in...

Sense flags in a memory device

Defective bit line management in connection with a memory access

Achieving consistent read times in multi-level non-volatile memory

One-sided soft reads

Program verification time reduction in non-volatile memory devices

Configuration of a memory device for programming memory cells

Erase and soft program for vertical NAND flash

Ramping inhibit voltage during memory programming

Method and system for reducing program disturb degradation in flash...

Transfer of encoded data stored in non-volatile memory for decoding...

Operation of a memory device during programming

Segmented erase in memory

Apparatus and method for mapping binary to ternary and its reverse

System and method for performing a concurrent multiple page read of...

Buffer operations in memory

Sense flags in a memory device

Apparatuses and methods for concurrently accessing multiple memory...

Data recovery in memory devices

Erase and soft program for vertical NAND flash

Method and apparatus for improving sequential reading in NAND flash

Patents Applicationslast 30 patents

FLASH MEMORY CHIP THAT MODULATES ITS PROGRAM STEP VOLTAGE AS A FUNC...

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

SYNCHRONOUS INDEPENDENT PLANE READ OPERATION

METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE...

METHOD AND APPARATUS FOR IMPROVING WRITE UNIFORMITY IN A MEMORY DEVICE

PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROV...

CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR...

SIMULTANEOUS PROGRAMMING OF MULTIPLE SUB-BLOCKS IN NAND MEMORY STRU...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...

STRING CURRENT REDUCTION DURING MULTISTROBE SENSING TO REDUCE READ...

FLASH MEMORY HAVING IMPROVED PERFORMANCE AS A CONSEQUENCE OF PROGRA...

FLASH MEMORY CHIP THAT MODULATES ITS PROGRAM STEP VOLTAGE AS A FUNC...

APPARATUSES, SYSTEMS, AND METHODS FOR HEATING A MEMORY DEVICE

DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS

VARIABLE ERROR CORRECTION CODEWORD PACKING TO SUPPORT BIT ERROR RAT...

DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH...

SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF...

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

SENSE FLAGS IN A MEMORY DEVICE

ACHIEVING CONSISTENT READ TIMES IN MULTI-LEVEL NON-VOLATILE MEMORY

ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...

STORAGE SYSTEM WITH RECONFIGURABLE NUMBER OF BITS PER CELL

RESUMING STORAGE DIE PROGRAMMING AFTER POWER LOSS

PROGRAM VERIFICATION TIME REDUCTION IN NON-VOLATILE MEMORY DEVICES

SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF...

ONE-SIDED SOFT READS

METHOD AND SYSTEM FOR REDUCING PROGRAM DISTURB DEGRADATION IN FLASH...