Prasad H. Chalasani

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-protocol receiver
- Patent number 10,791,203
- Issue date Sep 29, 2020
- Synopsys, Inc.
- Prasad Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus of operating synchronizing high-speed clock di...
- Patent number 10,505,550
- Issue date Dec 10, 2019
- Invecas, Inc.
- Shaolei Quan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital voltmeter
- Patent number 10,502,769
- Issue date Dec 10, 2019
- William Loh
- G01 - MEASURING TESTING
Information Patent Grant
Duty cycle detection
- Patent number 10,361,684
- Issue date Jul 23, 2019
- Invecas, Inc.
- Venkata N. S. N. Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage detector
- Patent number 10,094,859
- Issue date Oct 9, 2018
- Invecas, Inc.
- Venkata N. S. N. Rao
- G01 - MEASURING TESTING
Information Patent Grant
Clock alignment scheme for data macros of DDR PHY
- Patent number 10,014,866
- Issue date Jul 3, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimal data eye for improved Vref margin
- Patent number 9,971,975
- Issue date May 15, 2018
- Invecas, Inc.
- Venkata N. S. N. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock alignment scheme for data macros of DDR PHY
- Patent number 9,954,538
- Issue date Apr 24, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for clocking a physical layer interface
- Patent number 9,948,310
- Issue date Apr 17, 2018
- SOCTRONICS, INC.
- Prasad Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimal data eye for improved Vref margin
- Patent number 9,715,907
- Issue date Jul 25, 2017
- Invecas, Inc.
- Venkata N. S. N. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for clocking a physical layer interface
- Patent number 9,564,905
- Issue date Feb 7, 2017
- SOCTRONICS, INC.
- Prasad Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for distributing clock and reset signals across...
- Patent number 9,467,149
- Issue date Oct 11, 2016
- SOCTRONICS, INC.
- Prasad Chalasani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory interface
- Patent number 9,349,421
- Issue date May 24, 2016
- SOCTRONICS, INC.
- Venkata N. S. N. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip-flop circuit with reduced power consumption
- Patent number 6,864,732
- Issue date Mar 8, 2005
- Procket Networks, Inc.
- Prasad H. Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Multi-Protocol Receiver
- Publication number 20190132428
- Publication date May 2, 2019
- Invecas, Inc.
- Prasad Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Voltmeter
- Publication number 20190072589
- Publication date Mar 7, 2019
- Invecas, Inc.
- William Loh
- G01 - MEASURING TESTING
Information Patent Application
Duty Cycle Detection
- Publication number 20190028090
- Publication date Jan 24, 2019
- Invecas, Inc.
- Venkata N.S.N. Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Alignment Scheme for Data Macros of DDR PHY
- Publication number 20180006656
- Publication date Jan 4, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Alignment Scheme for Data Macros of DDR PHY
- Publication number 20170373696
- Publication date Dec 28, 2017
- Invecas, Inc.
- Narasimhan Vasudevan
- G11 - INFORMATION STORAGE
Information Patent Application
Optimal Data Eye for Improved Vref Margin
- Publication number 20170323222
- Publication date Nov 9, 2017
- Invecas, Inc.
- Venkata N.S.N. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Clocking a Physical Layer Interface
- Publication number 20160246325
- Publication date Aug 25, 2016
- SoCtronics, Inc.
- Prasad Chalasani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Interface
- Publication number 20150221350
- Publication date Aug 6, 2015
- KOOL CHIP, INC.
- Venkata N.S.N. Rao
- G11 - INFORMATION STORAGE
Information Patent Application
Delay Locked Loop
- Publication number 20140312945
- Publication date Oct 23, 2014
- Sharat Ippili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Distributing Clock and Reset Signals
- Publication number 20140317434
- Publication date Oct 23, 2014
- KOOL CHIP, INC.
- Prasad Chalasani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Clocking a Physical Layer Interface
- Publication number 20140314190
- Publication date Oct 23, 2014
- KOOL CHIP, INC.
- Prasad Chalasani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip-flop circuit with reduced power consumption
- Publication number 20040095175
- Publication date May 20, 2004
- Procket Networks, Inc.
- Prasad H. Chalasani
- H03 - BASIC ELECTRONIC CIRCUITRY

Prasad H. Chalasani

Person

Patents Grantslast 30 patents

Multi-protocol receiver

Method and apparatus of operating synchronizing high-speed clock di...

Digital voltmeter

Duty cycle detection

Voltage detector

Clock alignment scheme for data macros of DDR PHY

Optimal data eye for improved Vref margin

Clock alignment scheme for data macros of DDR PHY

Methods and systems for clocking a physical layer interface

Optimal data eye for improved Vref margin

Methods and systems for clocking a physical layer interface

Methods and systems for distributing clock and reset signals across...

Memory interface

Flip-flop circuit with reduced power consumption

Patents Applicationslast 30 patents

Multi-Protocol Receiver

Digital Voltmeter

Duty Cycle Detection

Clock Alignment Scheme for Data Macros of DDR PHY

Clock Alignment Scheme for Data Macros of DDR PHY

Optimal Data Eye for Improved Vref Margin

Methods and Systems for Clocking a Physical Layer Interface

Memory Interface

Delay Locked Loop

Methods and Systems for Distributing Clock and Reset Signals

Methods and Systems for Clocking a Physical Layer Interface

Flip-flop circuit with reduced power consumption