Prasad Subbarao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Closed-loop adaptive voltage scaling for integrated circuits
- Patent number 9,158,319
- Issue date Oct 13, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Grant
Methods for designing integrated circuits employing voltage scaling...
- Patent number 8,806,408
- Issue date Aug 12, 2014
- Agere Systems Inc.
- James C. Parker
- G01 - MEASURING TESTING
Information Patent Grant
Distributed delay prediction of multi-million gate deep sub-micron...
- Patent number 7,006,962
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Saket Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Driver waveform modeling with multiple effective capacitances
- Patent number 6,845,348
- Issue date Jan 18, 2005
- LSI Logic Corporation
- Prasad Subbarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bowtie and T-shaped structures of L-shaped mesh implementation
- Patent number 6,835,972
- Issue date Dec 28, 2004
- LSI Logic Corporation
- Radoslav Ratchkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for checking for power errors in ASIC designs
- Patent number 6,829,754
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Qiong J. Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupling capacitance estimation and insertion flow for ASIC designs
- Patent number 6,807,656
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Donut power mesh scheme for flip chip package
- Patent number 6,781,228
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Termination ring for integrated circuit
- Patent number 6,747,349
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Maad Al-Dabagh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
- Publication number 20150109052
- Publication date Apr 23, 2015
- LSI Corporation
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...
- Publication number 20140298277
- Publication date Oct 2, 2014
- James C. Parker
- G01 - MEASURING TESTING
Information Patent Application
CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTI...
- Publication number 20140028364
- Publication date Jan 30, 2014
- LSI Corporation
- Ramnath Venkatraman
- G01 - MEASURING TESTING
Information Patent Application
METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...
- Publication number 20100026378
- Publication date Feb 4, 2010
- Agere Systems, Inc.
- James C. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS
- Publication number 20040199882
- Publication date Oct 7, 2004
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Donut power mesh scheme for flip chip package
- Publication number 20040135263
- Publication date Jul 15, 2004
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bowtie and T-shaped structures of L-shaped mesh implementation
- Publication number 20040129955
- Publication date Jul 8, 2004
- Radoslav Ratchkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TERMINATION RING FOR INTEGRATED CIRCUIT
- Publication number 20040124521
- Publication date Jul 1, 2004
- Maad Al-Dabagh
- H01 - BASIC ELECTRIC ELEMENTS

Prasad Subbarao

Person

Patents Grantslast 30 patents

Closed-loop adaptive voltage scaling for integrated circuits

Methods for designing integrated circuits employing voltage scaling...

Distributed delay prediction of multi-million gate deep sub-micron...

Driver waveform modeling with multiple effective capacitances

Bowtie and T-shaped structures of L-shaped mesh implementation

Method and system for checking for power errors in ASIC designs

Decoupling capacitance estimation and insertion flow for ASIC designs

Donut power mesh scheme for flip chip package

Termination ring for integrated circuit

Patents Applicationslast 30 patents

CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...

CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTI...

METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING...

DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS

Donut power mesh scheme for flip chip package

Bowtie and T-shaped structures of L-shaped mesh implementation

TERMINATION RING FOR INTEGRATED CIRCUIT