Prasanna Parthasarathy

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic run time programming of hardware tables
- Patent number 11,301,231
- Issue date Apr 12, 2022
- Arista Networks, Inc.
- Prasanna Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical time stamping
- Patent number 11,233,720
- Issue date Jan 25, 2022
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method of a data processing pipeline with policy based r...
- Patent number 10,673,757
- Issue date Jun 2, 2020
- Arista Networks, Inc.
- Prasanna Parthasarathy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical time stamping
- Patent number 10,541,900
- Issue date Jan 21, 2020
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link aggregation split-brain detection and recovery
- Patent number 10,257,019
- Issue date Apr 9, 2019
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
EXECUTION OF MULTIPLE DISTINCT PIPELINES IN A SINGLE NETWORK DEVICE
- Publication number 20240275741
- Publication date Aug 15, 2024
- Arista Networks, Inc.
- Navdeep Bhatia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet Classification Using Lookup Tables with Different Key-widths
- Publication number 20240214309
- Publication date Jun 27, 2024
- Arista Networks, Inc.
- Michael Chih-Yen Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ASSOCIATING TAGS TO CONFIGURATION ITEMS FOR TAG-BASED CONFIGURATION...
- Publication number 20240143342
- Publication date May 2, 2024
- Arista Networks, Inc.
- Prasanna Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL TIME STAMPING
- Publication number 20220231934
- Publication date Jul 21, 2022
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC RUNTIME PROGRAMMING OF HARDWARE TABLES
- Publication number 20200319875
- Publication date Oct 8, 2020
- Arista Networks, Inc.
- Prasanna Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL TIME STAMPING
- Publication number 20200145314
- Publication date May 7, 2020
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD OF A DATA PROCESSING PIPELINE WITH POLICY BASED R...
- Publication number 20190372895
- Publication date Dec 5, 2019
- Arista Networks, Inc.
- Prasanna Parthasarathy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIERARCHICAL TIME STAMPING
- Publication number 20170222909
- Publication date Aug 3, 2017
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LINK AGGREGATION SPLIT-BRAIN DETECTION AND RECOVERY
- Publication number 20170163473
- Publication date Jun 8, 2017
- Arista Networks, Inc.
- Anshul Sadana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Prasanna Parthasarathy

Person

Patents Grantslast 30 patents

Dynamic run time programming of hardware tables

Hierarchical time stamping

System and method of a data processing pipeline with policy based r...

Hierarchical time stamping

Link aggregation split-brain detection and recovery

Patents Applicationslast 30 patents

EXECUTION OF MULTIPLE DISTINCT PIPELINES IN A SINGLE NETWORK DEVICE

Packet Classification Using Lookup Tables with Different Key-widths

ASSOCIATING TAGS TO CONFIGURATION ITEMS FOR TAG-BASED CONFIGURATION...

HIERARCHICAL TIME STAMPING

DYNAMIC RUNTIME PROGRAMMING OF HARDWARE TABLES

HIERARCHICAL TIME STAMPING

SYSTEM AND METHOD OF A DATA PROCESSING PIPELINE WITH POLICY BASED R...

HIERARCHICAL TIME STAMPING

LINK AGGREGATION SPLIT-BRAIN DETECTION AND RECOVERY