Prasant Vallur

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Clock gating using a cascaded clock gating control signal
- Patent number 12,088,296
- Issue date Sep 10, 2024
- Advanced Micro Devices, Inc.
- Ramon A. Mangaser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual phase clock distribution from a single source in a die-to-die...
- Patent number 12,015,412
- Issue date Jun 18, 2024
- Advanced Micro Devices, Inc.
- Srikanth Reddy Gruddanti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Skew matching in a die-to-die interface
- Patent number 11,960,435
- Issue date Apr 16, 2024
- Advanced Micro Devices, Inc.
- Pradeep Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive biasing circuit for serial communication interfaces
- Patent number 11,764,789
- Issue date Sep 19, 2023
- Advanced Micro Devices, Inc.
- Rajesh Mangalore Anand
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-voltage tolerant inverter
- Patent number 11,569,819
- Issue date Jan 31, 2023
- Advanced Micro Devices, Inc.
- Dhruvin Devangbhai Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High voltage output circuit with low voltage devices using data dep...
- Patent number 11,418,189
- Issue date Aug 16, 2022
- Advanced Micro Devices, Inc.
- Jagadeesh Anathahalli Singrigowda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate-source voltage generation for pull-up and pull-down devices in...
- Patent number 10,715,139
- Issue date Jul 14, 2020
- Advanced Micro Devices, Inc.
- Rajesh Mangalore Anand
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated differential clock gater
- Patent number 9,625,938
- Issue date Apr 18, 2017
- Advanced Micro Devices, Inc.
- Hariprasad Thodukattil Thazhatheppattu
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DUAL PHASE CLOCK DISTRIBUTION FROM A SINGLE SOURCE IN A DIE-TO-DIE...
- Publication number 20240186994
- Publication date Jun 6, 2024
- ADVANCED MICRO DEVICES, INC.
- SRIKANTH REDDY GRUDDANTI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SKEW MATCHING IN A DIE-TO-DIE INTERFACE
- Publication number 20230195678
- Publication date Jun 22, 2023
- ADVANCED MICRO DEVICES, INC.
- PRADEEP JAYARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATING USING A CASCADED CLOCK GATING CONTROL SIGNAL
- Publication number 20230198527
- Publication date Jun 22, 2023
- ADVANCED MICRO DEVICES, INC.
- RAMON A. MANGASER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE BIASING CIRCUIT FOR SERIAL COMMUNICATION INTERFACES
- Publication number 20230095805
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Rajesh Mangalore Anand
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH VOLTAGE OUTPUT CIRCUIT WITH LOW VOLTAGE DEVICES USING DATA DEP...
- Publication number 20210409020
- Publication date Dec 30, 2021
- ADVANCED MICRO DEVICES, INC.
- Jagadeesh Anathahalli Singrigowda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GATE-SOURCE VOLTAGE GENERATION FOR PULL-UP AND PULL-DOWN DEVICES IN...
- Publication number 20200076429
- Publication date Mar 5, 2020
- ADVANCED MICRO DEVICES, INC.
- Rajesh Mangalore Anand
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED DIFFERENTIAL CLOCK GATER
- Publication number 20160285437
- Publication date Sep 29, 2016
- Advanced Micro Devices, Inc.
- Hariprasad Thodukattil Thazhatheppattu
- G06 - COMPUTING CALCULATING COUNTING

Prasant Vallur

Person

Patents Grantslast 30 patents

Clock gating using a cascaded clock gating control signal

Dual phase clock distribution from a single source in a die-to-die...

Skew matching in a die-to-die interface

Adaptive biasing circuit for serial communication interfaces

High-voltage tolerant inverter

High voltage output circuit with low voltage devices using data dep...

Gate-source voltage generation for pull-up and pull-down devices in...

Integrated differential clock gater

Patents Applicationslast 30 patents

DUAL PHASE CLOCK DISTRIBUTION FROM A SINGLE SOURCE IN A DIE-TO-DIE...

SKEW MATCHING IN A DIE-TO-DIE INTERFACE

CLOCK GATING USING A CASCADED CLOCK GATING CONTROL SIGNAL

ADAPTIVE BIASING CIRCUIT FOR SERIAL COMMUNICATION INTERFACES

HIGH VOLTAGE OUTPUT CIRCUIT WITH LOW VOLTAGE DEVICES USING DATA DEP...

GATE-SOURCE VOLTAGE GENERATION FOR PULL-UP AND PULL-DOWN DEVICES IN...

INTEGRATED DIFFERENTIAL CLOCK GATER