Praveen Kumar Verma

Person

Greater Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
SRAM with fast, controlled peak current, power efficient array rese...
- Patent number 12,159,689
- Issue date Dec 3, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power and fast memory reset
- Patent number 12,068,026
- Issue date Aug 20, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory architecture with gated sub-array operation dependen...
- Patent number 12,046,324
- Issue date Jul 23, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory supporting a single clock cycle read-mo...
- Patent number 12,040,013
- Issue date Jul 16, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature compensated read assist circuit for a static random acc...
- Patent number 9,865,333
- Issue date Jan 9, 2018
- STMicroelectronics International N.V.
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BIT CELL BASED WRITE SELF-TIME DELAY PATH
- Publication number 20240331767
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM
- Publication number 20240331768
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY SUPPORTING A DYNAMICALLY VARIABLE DURAT...
- Publication number 20240170032
- Publication date May 23, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...
- Publication number 20230280915
- Publication date Sep 7, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WOR...
- Publication number 20230135708
- Publication date May 4, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...
- Publication number 20230050783
- Publication date Feb 16, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...
- Publication number 20230051672
- Publication date Feb 16, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20230018420
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER AND FAST MEMORY RESET
- Publication number 20230015002
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACC...
- Publication number 20170301396
- Publication date Oct 19, 2017
- STMicroelectronics International N.V
- Kedar Janardan Dhori
- G11 - INFORMATION STORAGE

Praveen Kumar Verma

Person

Patents Grantslast 30 patents

SRAM with fast, controlled peak current, power efficient array rese...

Low power and fast memory reset

Modular memory architecture with gated sub-array operation dependen...

Static random access memory supporting a single clock cycle read-mo...

Temperature compensated read assist circuit for a static random acc...

Patents Applicationslast 30 patents

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

BIT CELL BASED WRITE SELF-TIME DELAY PATH

BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM

STATIC RANDOM ACCESS MEMORY SUPPORTING A DYNAMICALLY VARIABLE DURAT...

STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...

MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WOR...

STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MO...

MODULAR MEMORY ARCHITECTURE WITH GATED SUB-ARRAY OPERATION DEPENDEN...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

LOW POWER AND FAST MEMORY RESET

TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACC...