Prithvi Shankar YEYYADI ANANTHA

Person

Bengaluru, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Fault detection in a real-time image pipeline
- Patent number 12,125,122
- Issue date Oct 22, 2024
- Texas Instruments Incorporated
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-channel system architecture for managing flow of data and ass...
- Patent number 12,111,780
- Issue date Oct 8, 2024
- Texas Instruments Incorporated
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory allocation for microcontroller execution
- Patent number 12,067,244
- Issue date Aug 20, 2024
- Texas Instruments Incorporated
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic mapping of data to lower latency memory based on data access
- Patent number 11,940,909
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Sriramakrishan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Permanent fault detection for imaging and vision hardware accelerators
- Patent number 11,715,188
- Issue date Aug 1, 2023
- Texas Instruments Incorporated
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault detectable and tolerant neural network
- Patent number 11,710,030
- Issue date Jul 25, 2023
- Texas Instmments Incorporated
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant communications for multi-chip systems
- Patent number 11,550,674
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Sriramakrishnan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Tracing for High Bandwidth Masters in SoC
- Publication number 20240427717
- Publication date Dec 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT DETECTION IN A REAL-TIME IMAGE PIPELINE
- Publication number 20240428365
- Publication date Dec 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO BOOT FROM BLOCK DEVICES
- Publication number 20240411563
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ALLOCATION FOR MICROCONTROLLER EXECUTION
- Publication number 20240370170
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MAPPING OF DATA TO LOWER LATENCY MEMORY BASED ON DATA ACCESS
- Publication number 20240248839
- Publication date Jul 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ALLOCATION FOR MICROCONTROLLER EXECUTION
- Publication number 20240176488
- Publication date May 30, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE SHARING ACROSS MULTIPLE CORES
- Publication number 20240037028
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kedar CHITNIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE MEMORY MIRRORING PERFORMANCE ACCELERATOR
- Publication number 20230342292
- Publication date Oct 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO BOOT FROM BLOCK DEVICES
- Publication number 20230333858
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERMANENT FAULT DETECTION FOR IMAGING AND VISION HARDWARE ACCELERATORS
- Publication number 20230326002
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tracing for High Bandwidth Masters in SoC
- Publication number 20230267084
- Publication date Aug 24, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT DETECTION IN A REAL-TIME IMAGE PIPELINE
- Publication number 20230196497
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT COMMUNICATIONS FOR MULTI-CHIP SYSTEMS
- Publication number 20230161675
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ORCHESTRATION OF MULTI-CORE MACHINE LEARNING PROCESSORS
- Publication number 20220391776
- Publication date Dec 8, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT COMMUNICATIONS FOR MULTI-CHIP SYSTEMS
- Publication number 20220138058
- Publication date May 5, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT DETECTABLE AND TOLERANT NEURAL NETWORK
- Publication number 20200074287
- Publication date Mar 5, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Narendra MODY
- G06 - COMPUTING CALCULATING COUNTING

Prithvi Shankar YEYYADI ANANTHA

Person

Patents Grantslast 30 patents

Fault detection in a real-time image pipeline

Multi-channel system architecture for managing flow of data and ass...

Memory allocation for microcontroller execution

Dynamic mapping of data to lower latency memory based on data access

Permanent fault detection for imaging and vision hardware accelerators

Fault detectable and tolerant neural network

Redundant communications for multi-chip systems

Patents Applicationslast 30 patents

Tracing for High Bandwidth Masters in SoC

FAULT DETECTION IN A REAL-TIME IMAGE PIPELINE

METHODS AND APPARATUS TO BOOT FROM BLOCK DEVICES

MEMORY ALLOCATION FOR MICROCONTROLLER EXECUTION

DYNAMIC MAPPING OF DATA TO LOWER LATENCY MEMORY BASED ON DATA ACCESS

MEMORY ALLOCATION FOR MICROCONTROLLER EXECUTION

SOFTWARE SHARING ACROSS MULTIPLE CORES

ADAPTIVE MEMORY MIRRORING PERFORMANCE ACCELERATOR

METHODS AND APPARATUS TO BOOT FROM BLOCK DEVICES

PERMANENT FAULT DETECTION FOR IMAGING AND VISION HARDWARE ACCELERATORS

Tracing for High Bandwidth Masters in SoC

FAULT DETECTION IN A REAL-TIME IMAGE PIPELINE

REDUNDANT COMMUNICATIONS FOR MULTI-CHIP SYSTEMS

ORCHESTRATION OF MULTI-CORE MACHINE LEARNING PROCESSORS

REDUNDANT COMMUNICATIONS FOR MULTI-CHIP SYSTEMS

FAULT DETECTABLE AND TOLERANT NEURAL NETWORK