Puneet Arora

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory view for non-volatile memory module
- Patent number 11,971,818
- Issue date Apr 30, 2024
- Cadence Design Systems, Inc.
- Steven L. Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control algorithm generator for non-volatile memory module
- Patent number 11,966,633
- Issue date Apr 23, 2024
- Cadence Design Systems, Inc.
- Steven L. Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction visibility frameworks implemented using artificial inte...
- Patent number 10,928,986
- Issue date Feb 23, 2021
- EMC IP Holding Company LLC
- Hung T. Dinh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation event reduction and power control during MBIST through c...
- Patent number 10,783,299
- Issue date Sep 22, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failing read count diagnostics for memory built-in self-test
- Patent number 10,593,419
- Issue date Mar 17, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-channel, programmable fuse control unit
- Patent number 10,504,607
- Issue date Dec 10, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic diagnostics analysis for memory built-in self-test
- Patent number 10,482,989
- Issue date Nov 19, 2019
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Register-transfer level design engineering change order strategy
- Patent number 10,395,747
- Issue date Aug 27, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and computer-readable media utilizing improved da...
- Patent number 10,387,599
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customizable built-in self-test testplans for memory units
- Patent number 10,319,459
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Wireless communication of print content and a mobile device identifier
- Patent number 10,216,464
- Issue date Feb 26, 2019
- Hewlett-Packard Development Company, L.P.
- Puneet Kumar Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test logic at register transfer level in an integrated circuit design
- Patent number 10,192,013
- Issue date Jan 29, 2019
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Print reservation
- Patent number 10,185,524
- Issue date Jan 22, 2019
- Hewlett-Packard Development Company, L.P.
- Dhanendra Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory built-in self-test logic in an integrated circuit design
- Patent number 10,095,822
- Issue date Oct 9, 2018
- Cadence Design Systems, Inc.
- Navneet Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated method identifying physical memories within a core or mac...
- Patent number 10,007,489
- Issue date Jun 26, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Marking agent credit adjustments
- Patent number 9,898,235
- Issue date Feb 20, 2018
- Hewlett-Packard Development Company, L.P.
- Shinoj Bhaskaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing error correction code (ECC) logic...
- Patent number 9,865,362
- Issue date Jan 9, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Reminder messages
- Patent number 9,715,680
- Issue date Jul 25, 2017
- Hewlett-Packard Development Company, L.P.
- Puneet Kumar Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power domain aware insertion methods and designs for testing and re...
- Patent number 9,640,280
- Issue date May 2, 2017
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Identification to access portable computing device
- Patent number 9,542,547
- Issue date Jan 10, 2017
- Hewlett-Packard Development Company, L.P.
- Shinoj Bhaskaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Near field communication data transfer
- Patent number 9,055,393
- Issue date Jun 9, 2015
- Hewlett-Packard Development Company, L.P.
- Puneet Kumar Arora
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,990,749
- Issue date Mar 24, 2015
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,719,761
- Issue date May 6, 2014
- Candence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost production testing for memory
- Patent number 8,677,196
- Issue date Mar 18, 2014
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing state retention logic in low power systems
- Patent number 8,271,226
- Issue date Sep 18, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PRINT RESERVATION
- Publication number 20170364315
- Publication date Dec 21, 2017
- Hewlett-Packard Development Company, L.P.
- Dhanendra Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRELESS COMMUNICATION OF PRINT CONTENT AND A MOBILE DEVICE IDENTIFIER
- Publication number 20160313954
- Publication date Oct 27, 2016
- Hewlett-Packard Development Company, L.P.
- Puneet Kumar Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MARKING AGENT CREDIT ADJUSTMENTS
- Publication number 20160070514
- Publication date Mar 10, 2016
- Hewlett-Packard Development Company, L.P.
- Shinoj Bhaskaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEAR FIELD COMMUNICATION DATA TRANSFER
- Publication number 20140302785
- Publication date Oct 9, 2014
- Hewlett-Packard Development Company, L.P.
- Puneet Kumar Arora
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089874
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089875
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMINDER MESSAGES
- Publication number 20140040919
- Publication date Feb 6, 2014
- Puneet Kumar Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Identification to Access Portable Computing Device
- Publication number 20130340073
- Publication date Dec 19, 2013
- Shinoj Bhaskaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS
- Publication number 20090326854
- Publication date Dec 31, 2009
- Cadence Design Systems, Inc.
- Krishna CHAKRAVADHANULA
- G01 - MEASURING TESTING

Puneet Arora

Person

Patents Grantslast 30 patents

Systems and methods for scan chain stitching

Memory view for non-volatile memory module

Control algorithm generator for non-volatile memory module

Transaction visibility frameworks implemented using artificial inte...

Simulation event reduction and power control during MBIST through c...

Failing read count diagnostics for memory built-in self-test

Multiple-channel, programmable fuse control unit

Dynamic diagnostics analysis for memory built-in self-test

Register-transfer level design engineering change order strategy

Systems, methods, and computer-readable media utilizing improved da...

Customizable built-in self-test testplans for memory units

Wireless communication of print content and a mobile device identifier

Test logic at register transfer level in an integrated circuit design

Print reservation

Memory built-in self-test logic in an integrated circuit design

Automated method identifying physical memories within a core or mac...

Marking agent credit adjustments

Method and apparatus for testing error correction code (ECC) logic...

Reminder messages

Power domain aware insertion methods and designs for testing and re...

Identification to access portable computing device

Near field communication data transfer

Method and apparatus for optimizing memory-built-in-self test

Method and apparatus for optimizing memory-built-in-self test

Low cost production testing for memory

Testing state retention logic in low power systems

Patents Applicationslast 30 patents

PRINT RESERVATION

WIRELESS COMMUNICATION OF PRINT CONTENT AND A MOBILE DEVICE IDENTIFIER

MARKING AGENT CREDIT ADJUSTMENTS

NEAR FIELD COMMUNICATION DATA TRANSFER

Method and Apparatus for Optimizing Memory-Built-In-Self Test

Method and Apparatus for Optimizing Memory-Built-In-Self Test

REMINDER MESSAGES

Identification to Access Portable Computing Device

TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS