Puneet Gupta

Person

LaJolla, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory write and read assistance using negative differential resist...
- Patent number 10,832,752
- Issue date Nov 10, 2020
- The Regents of the University of California
- Puneet Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate-length biasing for digital circuit optimization
- Patent number 9,202,003
- Issue date Dec 1, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 9,069,926
- Issue date Jun 30, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,949,768
- Issue date Feb 3, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,869,094
- Issue date Oct 21, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,756,555
- Issue date Jun 17, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,635,583
- Issue date Jan 21, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,490,043
- Issue date Jul 16, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-mask double-patterning lithography
- Patent number 8,415,089
- Issue date Apr 9, 2013
- The Regents of the University of California
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Scaling BFD sessions for neighbors using physical / sub-interface r...
- Patent number 8,289,839
- Issue date Oct 16, 2012
- Cisco Technology, Inc.
- Puneet Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for gate-length biasing using annotation data
- Patent number 8,185,865
- Issue date May 22, 2012
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-length biasing for digital circuit optimization
- Patent number 8,127,266
- Issue date Feb 28, 2012
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional forwarding detection on multilink bundled interfaces
- Patent number 8,111,611
- Issue date Feb 7, 2012
- Cisco Technology, Inc.
- Hitesh Kapoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tool for modifying mask design layout
- Patent number 8,103,981
- Issue date Jan 24, 2012
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for wafer topography-aware integrated circuit des...
- Patent number 8,024,675
- Issue date Sep 20, 2011
- Tela Innovations, Inc.
- Puneet Gupta
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for performing transistor-level static performanc...
- Patent number 7,865,856
- Issue date Jan 4, 2011
- Tela Innovations, Inc.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of designing a digital circuit by correlating different stat...
- Patent number 7,823,098
- Issue date Oct 26, 2010
- Tela Innovations, Inc.
- Cho W. Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for topography-aware reticle enhancement
- Patent number 7,814,456
- Issue date Oct 12, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Arrangement of fill unit elements in an integrated circuit intercon...
- Patent number 7,745,239
- Issue date Jun 29, 2010
- Tela Innovations, Inc.
- O. Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for finding an equivalent circuit representation...
- Patent number 7,743,349
- Issue date Jun 22, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reshaping a transistor gate in an integrated...
- Patent number 7,730,432
- Issue date Jun 1, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for integrated circuit optimization by using an o...
- Patent number 7,716,612
- Issue date May 11, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for placing layout objects in a standard-cell layout
- Patent number 7,640,522
- Issue date Dec 29, 2009
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for varying the starting conditions for a resolut...
- Patent number 7,627,849
- Issue date Dec 1, 2009
- Tela Innovations, Inc.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for correcting a mask design layout
- Patent number 7,614,032
- Issue date Nov 3, 2009
- The Regents of the Univerisity of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improved priority based connection establi...
- Patent number 7,532,574
- Issue date May 12, 2009
- Cisco Technology, Inc.
- Ashwin Madhwaraj
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for selecting connections to bump based on priori...
- Patent number 7,443,792
- Issue date Oct 28, 2008
- Cisco Technology, Inc.
- Sandeep Dhar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Gate-length biasing for digital circuit optimization
- Patent number 7,441,211
- Issue date Oct 21, 2008
- Blaze DFM, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of IC fabrication, IC mask fabrication and program product t...
- Patent number 7,353,492
- Issue date Apr 1, 2008
- International Business Machines Corporation
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Checking connectivity for point-to-multipoint connections
- Patent number 7,330,437
- Issue date Feb 12, 2008
- Cisco Technology, Inc.
- Puneet Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
RELIABLE AND FAULT-TOLERANT CLOCK GENERATION AND DISTRIBUTION FOR C...
- Publication number 20240385643
- Publication date Nov 21, 2024
- The Regents of the University of California
- Puneet GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE MEMORY POOL SYSTEM
- Publication number 20240184738
- Publication date Jun 6, 2024
- The Regents of the University of California
- Saptadeep PAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WRITE AND READ ASSISTANCE USING NEGATIVE DIFFERENTIAL RESIST...
- Publication number 20190198079
- Publication date Jun 27, 2019
- The Regents of the University of California
- Puneet GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20140245245
- Publication date Aug 28, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gate-Length Biasing for Digital Circuit Optimization
- Publication number 20140223404
- Publication date Aug 7, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cells having transistors annotated for gate-length biasing
- Publication number 20130254734
- Publication date Sep 26, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014072
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014073
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014071
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA
- Publication number 20100169846
- Publication date Jul 1, 2010
- Tela Innovations. Inc., a Delaware Corporation
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20100169847
- Publication date Jul 1, 2010
- Tela Innovations. Inc., a Delaware Corporation
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOOL FOR MODIFYING MASK DESIGN LAYOUT
- Publication number 20100023917
- Publication date Jan 28, 2010
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bidirectional Forwarding Detection on Multilink Bundled Interfaces
- Publication number 20090323520
- Publication date Dec 31, 2009
- Cisco Technology, Inc., a coporation of California
- Hitesh Kapoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Scaling BFD sessions for neighbors using physical / sub-interface r...
- Publication number 20090010171
- Publication date Jan 8, 2009
- Cisco Technology, Inc.
- Puneet Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for correcting a mask design layout
- Publication number 20070168903
- Publication date Jul 19, 2007
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for detailed placement of layout objects in a sta...
- Publication number 20070168898
- Publication date Jul 19, 2007
- BLAZE DFM, INC.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for finding an equivalent circuit representation...
- Publication number 20060150132
- Publication date Jul 6, 2006
- BLAZE-DFM, INC.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for topography-aware reticle enhancement
- Publication number 20060110837
- Publication date May 25, 2006
- BLAZE DFM, INC.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method and system for selecting connections to bump based on priori...
- Publication number 20060045095
- Publication date Mar 2, 2006
- Sandeep Dhar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method of IC fabrication, IC mask fabrication and program product t...
- Publication number 20050193363
- Publication date Sep 1, 2005
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Integrated circuit logic with self compensating block delays
- Publication number 20050189604
- Publication date Sep 1, 2005
- Puneet Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for correcting a mask design layout
- Publication number 20040237061
- Publication date Nov 25, 2004
- The Regents of the University of California.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for use of an application state storage system...
- Publication number 20030163393
- Publication date Aug 28, 2003
- Sanjay Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for use of an application state storage system...
- Publication number 20010027483
- Publication date Oct 4, 2001
- Puneet Kumar Gupta
- G06 - COMPUTING CALCULATING COUNTING

Puneet Gupta

Person

Patents Grantslast 30 patents

Memory write and read assistance using negative differential resist...

Gate-length biasing for digital circuit optimization

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Single-mask double-patterning lithography

Scaling BFD sessions for neighbors using physical / sub-interface r...

Methods for gate-length biasing using annotation data

Gate-length biasing for digital circuit optimization

Bidirectional forwarding detection on multilink bundled interfaces

Tool for modifying mask design layout

Method and system for wafer topography-aware integrated circuit des...

System and method for performing transistor-level static performanc...

Method of designing a digital circuit by correlating different stat...

Method and system for topography-aware reticle enhancement

Arrangement of fill unit elements in an integrated circuit intercon...

Method and system for finding an equivalent circuit representation...

Method and system for reshaping a transistor gate in an integrated...

Method and system for integrated circuit optimization by using an o...

Method and system for placing layout objects in a standard-cell layout

System and method for varying the starting conditions for a resolut...

Method for correcting a mask design layout

Method and apparatus for improved priority based connection establi...

Method and system for selecting connections to bump based on priori...

Gate-length biasing for digital circuit optimization

Method of IC fabrication, IC mask fabrication and program product t...

Checking connectivity for point-to-multipoint connections

Patents Applicationslast 30 patents

RELIABLE AND FAULT-TOLERANT CLOCK GENERATION AND DISTRIBUTION FOR C...

CONFIGURABLE MEMORY POOL SYSTEM

MEMORY WRITE AND READ ASSISTANCE USING NEGATIVE DIFFERENTIAL RESIST...

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

Gate-Length Biasing for Digital Circuit Optimization

Standard Cells having transistors annotated for gate-length biasing

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

TOOL FOR MODIFYING MASK DESIGN LAYOUT

Bidirectional Forwarding Detection on Multilink Bundled Interfaces

Scaling BFD sessions for neighbors using physical / sub-interface r...

Method for correcting a mask design layout

Method and system for detailed placement of layout objects in a sta...

Method and system for finding an equivalent circuit representation...

Method and system for topography-aware reticle enhancement

Method and system for selecting connections to bump based on priori...

Method of IC fabrication, IC mask fabrication and program product t...

Integrated circuit logic with self compensating block delays

Method for correcting a mask design layout

Method and apparatus for use of an application state storage system...

Method and apparatus for use of an application state storage system...